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soc/intel/tigerlake: Delete unused configuration 

Delete below configuration
- Heci3Enabled: deprecated,
  see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442
- PchIshEnable: don't need as it's handled by devicetree dev on/off,
  see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87

BUG🅱️151166877
BRANCH=none
TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wonkyu Kim 2020-05-20 13:25:04 -07:00 committed by Patrick Georgi
parent 165efa1b86
commit b4d7116a74
1 changed files with 0 additions and 6 deletions
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6
src/soc/intel/tigerlake/chip.h
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@ -136,12 +136,6 @@ struct soc_intel_tigerlake_config {
/* SMBus */ /* SMBus */
uint8_t SmbusEnable; uint8_t SmbusEnable;
/* Integrated Sensor */
uint8_t PchIshEnable;
/* Heci related */
uint8_t Heci3Enabled;
/* Gfx related */ /* Gfx related */
uint8_t IgdDvmt50PreAlloc; uint8_t IgdDvmt50PreAlloc;
uint8_t InternalGfx; uint8_t InternalGfx;