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mb/prodrive/hermes: Rework UART devicetree entry 

Rework the UART devicetree entry so that it doesn't conflict with the
to-be-added chipset devicetree for CNL. This should be functionally
equivalent to the previous entry, but needs testing to verify.

Change-Id: Iae60cb8e0746e7dc2928da3687762b81928fb5f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78546
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Matt DeVillier 2023-10-22 12:10:35 -05:00 committed by Martin L Roth
parent 14701fb6a6
commit b9165199c3
1 changed files with 5 additions and 4 deletions
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9
src/mainboard/prodrive/hermes/devicetree.cb
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@ -170,11 +170,12 @@ chip soc/intel/cannonlake
# This device does not have any function on CNP-H, but it needs # This device does not have any function on CNP-H, but it needs
# to be here so that the resource allocator is aware of UART 2. # to be here so that the resource allocator is aware of UART 2.
device pci 19.0 hidden end device pci 19.0 hidden end
chip soc/intel/common/block/uart device pci 19.2 hidden
device pci 19.2 hidden chip soc/intel/common/block/uart
register "devid" = "PCI_DID_INTEL_CNP_H_UART2" register "devid" = "PCI_DID_INTEL_CNP_H_UART2"
end # UART #2, in ACPI mode device generic 0 hidden end
end end
end # UART #2, in ACPI mode
device pci 1b.4 on # PCIe root port 21 (Slot 1) device pci 1b.4 on # PCIe root port 21 (Slot 1)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
register "PcieRpEnable[20]" = "1" register "PcieRpEnable[20]" = "1"