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mb/intel/adlrvp: Enable SaGv support 

BUG=b:187446498
TEST=Boot and verify memory trains at all the SaGv points through FSP
debug logs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
V Sowmya 2021-05-19 09:42:23 +05:30 committed by Subrata Banik
parent 1d19432e1e
commit c398a204b4
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/intel/adlrvp/devicetree.cb
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@ -16,6 +16,9 @@ chip soc/intel/alderlake
# Enable CNVi BT
register "CnviBtCore" = "true"
# Sagv Configuration
register "SaGv" = "SaGv_Enabled"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3