post_code: add post code for video initialization failure
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon initialization returns an error when graphics was also initialized. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -21,6 +21,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
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0xe2 Vendor binary (e.g. FSP) generated a fatal error
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0xe3 RAM could not be initialized
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0xe4 Critical hardware component could not initialize
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0xe5 Video subsystem failed to initialize
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0xf8 Entry into elf boot
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0xf3 Jumping to payload
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@ -18,6 +18,7 @@
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <program_loading.h>
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#include <soc/intel/common/vbt.h>
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#include <stage_cache.h>
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#include <string.h>
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#include <timestamp.h>
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@ -29,6 +30,7 @@ static void do_silicon_init(struct fsp_header *hdr)
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FSPS_UPD *upd, *supd;
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fsp_silicon_init_fn silicon_init;
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uint32_t status;
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uint8_t postcode;
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supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
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@ -59,8 +61,18 @@ static void do_silicon_init(struct fsp_header *hdr)
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/* Handle any errors returned by FspSiliconInit */
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fsp_handle_reset(status);
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if (status != FSP_SUCCESS) {
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if (vbt_get()) {
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/* Attempted to initialize graphics. Assume failure
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* is related to a video failure.
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*/
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postcode = POST_VIDEO_FAILURE;
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} else {
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/* Other silicon initialization failed */
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postcode = POST_HW_INIT_FAILURE;
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}
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printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
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die("FspSiliconINit returned an error!\n");
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die_with_post_code(postcode,
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"FspSiliconINit returned an error!\n");
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}
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}
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@ -355,6 +355,13 @@
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*/
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#define POST_HW_INIT_FAILURE 0xe4
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/**
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* \brief Video failure
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*
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* Video subsystem failed to initialize.
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*/
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#define POST_VIDEO_FAILURE 0xe5
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/**
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* \brief TPM failure
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*
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