soc/intel/meteorlake: Account for GSPI2 everywhere
Commit e54a8fd432
(soc/intel/meteorlake:
Add entry for GSPI2 device) added an entry for the GSPI2 device in the
devicetree, but did not add any other entries. Ensure that the rest of
the code is aware of the GSPI2 device to avoid any problems.
Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0
Found-by: Coverity CID 1490681
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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@ -101,6 +101,7 @@ const char *soc_acpi_name(const struct device *dev)
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case PCI_DEVFN_UART2: return "UAR2";
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case PCI_DEVFN_GSPI0: return "SPI0";
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case PCI_DEVFN_GSPI1: return "SPI1";
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case PCI_DEVFN_GSPI2: return "SPI2";
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/* Keeping ACPI device name coherent with ec.asl */
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case PCI_DEVFN_ESPI: return "LPCB";
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case PCI_DEVFN_HDA: return "HDAS";
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@ -59,6 +59,7 @@ static const pci_devfn_t i2c_dev[] = {
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static const pci_devfn_t gspi_dev[] = {
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PCI_DEVFN_GSPI0,
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PCI_DEVFN_GSPI1,
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PCI_DEVFN_GSPI2,
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};
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static const pci_devfn_t uart_dev[] = {
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@ -10,6 +10,8 @@ int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
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return PCI_DEVFN_GSPI0;
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case 1:
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return PCI_DEVFN_GSPI1;
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case 2:
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return PCI_DEVFN_GSPI2;
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}
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return -1;
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}
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@ -84,8 +84,10 @@
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#define PCI_DEV_SLOT_ISH 0x12
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#define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0)
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#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6)
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#define PCI_DEVFN_UFS _PCI_DEVFN(ISH, 7)
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#define PCI_DEV_ISH _PCI_DEV(ISH, 0)
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#define PCI_DEV_GSPI2 _PCI_DEV(ISH, 6)
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#define PCI_DEV_UFS _PCI_DEV(ISH, 7)
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#define PCI_DEV_SLOT_IOE 0x13
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@ -15,6 +15,8 @@ int spi_soc_devfn_to_bus(unsigned int devfn)
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return 1;
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case PCI_DEVFN_GSPI1:
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return 2;
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case PCI_DEVFN_GSPI2:
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return 3;
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}
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return -1;
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}
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