mainboard/amd/serengeti_cheetah: Fix coding style
Change-Id: I380368873e0508c3a55ac1c4ea0de172e675cf3a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -57,7 +57,7 @@ unsigned long acpi_fill_madt(unsigned long current)
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
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res->base, gsi_base );
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res->base, gsi_base);
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gsi_base+=7;
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}
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@ -67,7 +67,7 @@ unsigned long acpi_fill_madt(unsigned long current)
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
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res->base, gsi_base );
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res->base, gsi_base);
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gsi_base+=7;
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}
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}
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@ -75,9 +75,10 @@ unsigned long acpi_fill_madt(unsigned long current)
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int i;
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int j = 0;
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for(i = 1; i< sysconf.hc_possible_num; i++) {
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for (i = 1; i < sysconf.hc_possible_num; i++) {
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u32 d = 0;
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if(!(sysconf.pci1234[i] & 0x1) ) continue;
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if (!(sysconf.pci1234[i] & 0x1))
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continue;
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/* 8131 need to use +4 */
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switch (sysconf.hcid[i]) {
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case 1:
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@ -95,7 +96,7 @@ unsigned long acpi_fill_madt(unsigned long current)
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
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res->base, gsi_base );
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res->base, gsi_base);
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gsi_base+=d;
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}
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}
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@ -104,7 +105,7 @@ unsigned long acpi_fill_madt(unsigned long current)
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
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res->base, gsi_base );
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res->base, gsi_base);
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gsi_base+=d;
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}
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@ -116,7 +117,7 @@ unsigned long acpi_fill_madt(unsigned long current)
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}
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current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 5 );
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current, 0, 0, 2, 5);
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/* 0: mean bus 0--->ISA */
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/* 0: PIC 0 */
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/* 2: APIC 2 */
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@ -147,16 +148,15 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp
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/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
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for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
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for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
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const char *file_name;
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if((sysconf.pci1234[i] & 1) != 1 ) continue;
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if ((sysconf.pci1234[i] & 1) != 1)
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continue;
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u8 c;
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if(i < 7) {
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if (i < 7)
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c = (u8) ('4' + i - 1);
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}
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else {
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else
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c = (u8) ('A' + i - 1 - 6);
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}
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current = ALIGN(current, 8);
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printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */
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ssdtx = (acpi_header_t *)current;
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@ -49,24 +49,23 @@ static void *smp_write_config_table(void *v)
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dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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if (res)
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smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
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res2mmio(res, 0, 0));
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}
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}
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dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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if (res)
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smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
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res2mmio(res, 0, 0));
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}
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}
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j = 0;
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for(i = 1; i< sysconf.hc_possible_num; i++) {
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if(!(sysconf.pci1234[i] & 0x1) ) continue;
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for (i = 1; i < sysconf.hc_possible_num; i++) {
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if (!(sysconf.pci1234[i] & 0x1))
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continue;
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switch(sysconf.hcid[i]) {
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case 1: /* 8132 */
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@ -74,18 +73,16 @@ static void *smp_write_config_table(void *v)
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dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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if (res)
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smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
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res2mmio(res, 0, 0));
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}
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}
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dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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if (res)
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smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
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res2mmio(res, 0, 0));
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}
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}
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break;
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}
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@ -104,32 +101,29 @@ static void *smp_write_config_table(void *v)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
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/*Slot 3 PCI 32 */
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for(i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
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}
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/* Slot 4 PCI 32 */
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for(i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
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}
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/* Slot 1 PCI-X 133/100/66 */
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for(i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4);
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}
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/* Slot 2 PCI-X 133/100/66 */
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for(i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
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}
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j = 0;
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for(i = 1; i< sysconf.hc_possible_num; i++) {
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if(!(sysconf.pci1234[i] & 0x1) ) continue;
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for (i = 1; i < sysconf.hc_possible_num; i++) {
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if (!(sysconf.pci1234[i] & 0x1))
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continue;
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int ii;
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device_t dev;
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struct resource *res;
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@ -141,9 +135,8 @@ static void *smp_write_config_table(void *v)
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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/* Slot 1 PCI-X 133/100/66 */
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for(ii = 0; ii < 4; ii++) {
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for (ii = 0; ii < 4; ii++)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4);
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}
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}
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}
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@ -152,9 +145,8 @@ static void *smp_write_config_table(void *v)
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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/* Slot 2 PCI-X 133/100/66 */
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for(ii = 0; ii < 4; ii++) {
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for (ii = 0; ii < 4; ii++)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */
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}
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}
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}
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