mb/google/auron: Add SATA PCI device to overridetree

`chip` entries are only hooked up via device nodes to the tree. A `chip`
without a `device` below it does nothing. To allow variants to override
SATA tuning parameters, ensure a device exists under the PCH chip scope.

Without this change, some variants would not properly override the SATA
tuning parameters after extracting the PCH parts into a different chip.

TEST=Sanity-check static.c and verify overridetrees override properly.

Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46769
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/auron/variants/auron_paine/overridetree.cb

@@ -12,6 +12,8 @@ chip soc/intel/broadwell
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
+
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end

src/mainboard/google/auron/variants/auron_yuna/overridetree.cb

@@ -12,6 +12,8 @@ chip soc/intel/broadwell
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x7"
 			register "sata_port1_gen3_dtle" = "0x5"
+
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end

src/mainboard/google/auron/variants/buddy/overridetree.cb

@@ -34,6 +34,7 @@ chip soc/intel/broadwell
 			device pci 1c.0 off end # PCIe Port #1
 			device pci 1c.2 on  end # PCIe Port #3 - LAN (becomes RP1)
 			device pci 1c.3 on  end # PCIe Port #4 - WLAN (becomes RP2)
+			device pci 1f.2 on  end # SATA Controller
 			device pci 1f.3 on  end # SMBus
 #		end
 	end

src/mainboard/google/auron/variants/gandof/overridetree.cb

@@ -12,6 +12,8 @@ chip soc/intel/broadwell
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
+
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end

src/mainboard/google/auron/variants/lulu/overridetree.cb

@@ -12,6 +12,8 @@ chip soc/intel/broadwell
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
+
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end

src/mainboard/google/auron/variants/samus/overridetree.cb

@@ -36,6 +36,7 @@ chip soc/intel/broadwell
 			device pci 1c.0 off end # PCIe Port #1
 			device pci 1c.2 on  end # PCIe Port #3
 			device pci 1d.0 off end # USB2 EHCI
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end