soc/amd/picasso/cpu: move get_cpu_count to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y)
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bootblock-y += pre_c.S
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bootblock-y += write_resume_eip.c
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romstage-y += memmap.c
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ramstage-y += cpu.c
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ramstage-y += memmap.c
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endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/cpu.h>
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#include <cpu/cpu.h>
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int get_cpu_count(void)
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{
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return 1 + (cpuid_ecx(0x80000008) & 0xff);
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}
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@ -3,6 +3,7 @@
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#ifndef AMD_BLOCK_CPU_H
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#define AMD_BLOCK_CPU_H
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int get_cpu_count(void);
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void write_resume_eip(void);
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#endif /* AMD_BLOCK_CPU_H */
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@ -19,9 +19,9 @@
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#include <device/pci.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/cpu.h>
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#include <soc/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/southbridge.h>
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#include <soc/nvs.h>
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@ -12,7 +12,7 @@
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <soc/cpu.h>
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#include <amdblocks/cpu.h>
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#include <soc/data_fabric.h>
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#include <soc/pci_devs.h>
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#include <stdlib.h>
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/cpu.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/mtrr.h>
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@ -41,11 +42,6 @@ static void pre_mp_init(void)
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x86_mtrr_check();
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}
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int get_cpu_count(void)
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{
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return 1 + (cpuid_ecx(0x80000008) & 0xff);
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}
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static void set_cstate_io_addr(void)
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{
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msr_t cst_addr;
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@ -3,7 +3,6 @@
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#ifndef AMD_PICASSO_CPU_H
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#define AMD_PICASSO_CPU_H
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int get_cpu_count(void);
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void check_mca(void);
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#define RAVEN1_B0_CPUID 0x00810f10
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