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sb/intel/i82801gx: Add whitespace around '<<' 

Change-Id: I8ea8fdb031c09aac9ed4a0705c3204f87aadb565
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2017-07-03 21:35:58 +02:00 committed by Werner Zeh
parent 43927bae18
commit ddb64d33a0
2 changed files with 4 additions and 4 deletions
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4
src/southbridge/intel/i82801gx/smi.c
View File

@ -232,9 +232,9 @@ static u32 reset_tco_status(void)
reg32 = inl(tcobase + 0x04); reg32 = inl(tcobase + 0x04);
/* set status bits are cleared by writing 1 to them */ /* set status bits are cleared by writing 1 to them */
outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
if (reg32 & (1 << 18)) if (reg32 & (1 << 18))
outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS
return reg32; return reg32;
} }

4
src/southbridge/intel/i82801gx/smihandler.c
View File

@ -248,9 +248,9 @@ static u32 reset_tco_status(void)
reg32 = inl(tcobase + 0x04); reg32 = inl(tcobase + 0x04);
/* set status bits are cleared by writing 1 to them */ /* set status bits are cleared by writing 1 to them */
outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
if (reg32 & (1 << 18)) if (reg32 & (1 << 18))
outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS
return reg32; return reg32;
} }