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mb/siemens/mc_ehl2: Enable Marvell PHY interrupt 

On this mainboard Marvell PHY INTn is routed to LED[2] pin.

Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2022-11-10 09:46:17 +01:00 committed by Martin L Roth
parent 155cf5cd2e
commit e19f403770
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
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@ -189,6 +189,8 @@ chip soc/intel/elkhartlake
register "led_0_ctrl" = "7" register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link # LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1" register "led_1_ctrl" = "1"
# INTn is routed to LED[2] pin
register "enable_int" = "true"
device mdio 0 on # PHY address device mdio 0 on # PHY address
ops m88e1512_ops ops m88e1512_ops
end end
@ -202,6 +204,8 @@ chip soc/intel/elkhartlake
register "led_0_ctrl" = "7" register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link # LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1" register "led_1_ctrl" = "1"
# INTn is routed to LED[2] pin
register "enable_int" = "true"
device mdio 1 on # PHY address device mdio 1 on # PHY address
ops m88e1512_ops ops m88e1512_ops
end end
@ -218,6 +222,8 @@ chip soc/intel/elkhartlake
register "led_0_ctrl" = "7" register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link # LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1" register "led_1_ctrl" = "1"
# INTn is routed to LED[2] pin
register "enable_int" = "true"
device mdio 1 on # PHY address device mdio 1 on # PHY address
ops m88e1512_ops ops m88e1512_ops
end end