cpubug is fine.
adding vsm support now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
316ea53e29
commit
e4ad801495
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@ -5,3 +5,4 @@ dir /cpu/x86/lapic
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dir /cpu/x86/cache
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driver model_gx2_init.o
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object cpubug.o
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object vsmsetup.o
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@ -1,42 +1,16 @@
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#include <cpu/amd/model_gx2/gx2def.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include <cpu/amd/gx2def.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/cache.h>
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void
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cpubug(void){
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msr_t msr;
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int rev;
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msr = rdmsr(GLCP_CHIP_REVID);
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rev = msr.lo & 0xff;
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if (rev < 0x20) {
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printk_error("%s: rev < 0x20! bailing!\n");
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return;
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}
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switch(rev)
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{
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case 0x20:
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pcideadlock();
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eng1398();
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bug752();
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break;
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case 0x22:
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pcideadlock();
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eng1398();
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eng2900();
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bug 118339();
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break;
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case 0x22:
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case 0x30:
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break;
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default:
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printk_error("unknown rev %x, bailing\n", rev);
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return;
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}
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bug784();
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bug118253();
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disablememoryreadorder();
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}
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#if 0
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void
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@ -55,6 +29,7 @@ bug573(void){
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msr.eax &= 0xfff3;
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wrmsr(MC_GLD_MSR_PM);
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}
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#endif
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static void
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pcideadlock(void){
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@ -77,28 +52,29 @@ pcideadlock(void){
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/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
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msr.lo = 0x021212121;
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msr.hi = 0x021212121
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msr.hi = 0x021212121;
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wrmsr( CPU_RCONF_A0_BF, msr);
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wrmsr( CPU_RCONF_C0_DF, msr);
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wrmsr( CPU_RCONF_E0_FF, msr);
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}
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;**************************************************************************
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;*
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;* CPUbug784
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;*
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;* Bugtool #784 + #792
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;*
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;* Fix CPUID instructions for < 3.0 CPUs
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;*
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;* Entry:
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;* Exit:
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;* Modified:
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;*
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;**************************************************************************
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/****************************************************************************/
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/***/
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/** CPUbug784*/
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/***/
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/** Bugtool #784 + #792*/
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/***/
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/** Fix CPUID instructions for < 3.0 CPUs*/
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/***/
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/** Entry:*/
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/** Exit:*/
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/** Modified:*/
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/***/
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/****************************************************************************/
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void cpubug784(void){
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static char *name = "Geode by NSC";
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void bug784(void){
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msr_t msr;
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// static char *name = "Geode by NSC";
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/* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
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* would do this -- the OS can figure this type of stuff out!
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@ -113,9 +89,9 @@ void cpubug784(void){
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wrmsr(0x3007, msr);
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msr = rdmsr(0x3002);
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wrmsr(*0x3008, msr);
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wrmsr(0x3008, msr);
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; More CPUID to match AMD better. #792
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/* More CPUID to match AMD better. #792*/
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msr = rdmsr(0x3009);
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msr.hi = 0x0C0C0A13D;
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msr.lo = 0x00000000;
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@ -130,7 +106,7 @@ eng1398(void){
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msr = rdmsr(MSR_GLCP+0x17);
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if ((msr.lo & 0xff) < CPU_REV_2_0) {
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msr = rdmsr(GLCP_SYS_RSTPLL);
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i if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
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if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
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return;
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}
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@ -141,7 +117,7 @@ eng1398(void){
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}
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void
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eng2900{void){
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eng2900(void){
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printk_err(" NOT DOING eng2900: only shown to be a windows problem\n");
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#if 0
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@ -253,13 +229,14 @@ CPUbugIAENG2900 ENDP
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#endif
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}
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void eng118253(void){
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void bug118253(void){
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msr_t msr;
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msr = rdmsr(GLPCI_SPARE);
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msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
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wrmsr(GLPCI_SPARE, msr);
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}
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void
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bug118339(void) {
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printk_err("This is OPTIONAL BIOS-ENABLED ... ignore for now\n");
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@ -355,10 +332,50 @@ CPUbug118339 ENDP
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/***/
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/****************************************************************************/
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void
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DisableMemoryReorder(void) {
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disablememoryreadorder(void) {
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msr_t msr;
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msr = rdmsr(MC_CF8F_DATA);
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msr.hi |= CF8F_UPPER_REORDER_DIS_SET);
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msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
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wrmsr(MC_CF8F_DATA, msr);
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}
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void
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cpubug(void){
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msr_t msr;
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int rev;
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msr = rdmsr(GLCP_CHIP_REVID);
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rev = msr.lo & 0xff;
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if (rev < 0x20) {
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printk_err("%s: rev < 0x20! bailing!\n");
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return;
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}
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printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
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switch(rev)
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{
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case 0x20:
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pcideadlock();
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eng1398();
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/* cs 5530 bug; ignore
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bug752();
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*/
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break;
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case 0x21:
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pcideadlock();
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eng1398();
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eng2900();
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bug118339();
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break;
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case 0x22:
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case 0x30:
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break;
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default:
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printk_err("unknown rev %x, bailing\n", rev);
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return;
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}
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bug784();
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bug118253();
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disablememoryreadorder();
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printk_debug("Done cpubug fixes \n");
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}
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@ -145,7 +145,7 @@ setup_gx2_cache(int sizem)
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msr.lo = val;
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msr.hi = (val >> 32);
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printk_debug("msr will be set to %x:%x\n", msr.hi, msr.lo);
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wrmsr(0x1808, msr);
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wrmsr(CPU_RCONF_DEFAULT, msr);
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enable_cache();
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wbinvd();
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@ -164,6 +164,7 @@ setup_gx2(void)
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membytes = sizem * 1048576;
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/* we need to set 0x10000029 and 0x40000029 */
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msr.hi = 0x20000000 | membytes >>20;
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msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
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msr = rdmsr(0x40000029);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
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/* need to write 10000028 for vsm */
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/* it is a P2D_R, but the two we just wrote have same offset; use same value */
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wrmsr(0x10000028, msr);
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msr = rdmsr(0x10000028);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
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/* now do the default MSR values */
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for(i = 0; msr_defaults[i].msr_no; i++) {
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msr_t msr;
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printk_debug("gx2 north: enable_dev\n");
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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extern void cpubug(void);
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printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
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/* cpubug MUST be called before setup_gx2(), so we force the issue here */
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cpubug();
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setup_gx2();
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dev->ops = &pci_domain_ops;
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pci_set_method(dev);
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}
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else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
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dev->ops = &cpu_bus_ops;
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}
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@ -108,6 +108,7 @@ static const unsigned char pci33_ddr_crt [] = {
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26, 2, 3 // 433/289
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};
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#if 0
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static unsigned int get_memory_speed(void)
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{
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unsigned char val, hi, lo;
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return 20000/(hi*10 + lo);
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}
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#endif
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static void pll_reset(void)
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{
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