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mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device 

Setting the clock source depends on clock request pin for WLAN/SD/SSD
device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim,
clock source 0/1/2 are routed for WLAN/SD/SSD device.

BUG=b:227297986
BRANCH=none
TEST=Build

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Chris.Wang 2022-04-01 14:53:39 +08:00 committed by Felix Held
parent 4fdd84e716
commit ec7a932aa2
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
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@ -47,6 +47,12 @@ chip soc/amd/sabrina
register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR
register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC
# general purpose PCIe clock output configuration
register "gpp_clk_config[0]" = "GPP_CLK_REQ"
register "gpp_clk_config[1]" = "GPP_CLK_REQ"
register "gpp_clk_config[2]" = "GPP_CLK_REQ"
register "gpp_clk_config[3]" = "GPP_CLK_OFF"
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
device domain 0 on device domain 0 on