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google/veyron_*: Increase SPI flash frequency to 24.75MHz 

This patch increases the SPI clock for the ROM to 24.75MHz on all rk3288
(veyron) boards. This increases flash read speeds (and thereby decreases
boot time) significantly, but we don't seem to get any more increases by
going even higher. We have also seen occasional read failures at higher
speeds in certain configurations, so this frequency seems to be the best
option.

BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted on Jerry with Servo attached.

Change-Id: I9bdb62eff169fe2be33558caafe9891668589372
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a1d07da4266f2922b076dfae8396c24c6a84252b
Original-Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262645
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner 2015-03-24 16:54:38 -07:00 committed by Patrick Georgi
parent 2fdc61af6e
commit ee426cf54e
7 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/veyron_brain/bootblock.c
View File

@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
setup_chromeos_gpios();
}

2
src/mainboard/google/veyron_danger/bootblock.c
View File

@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
setup_chromeos_gpios();
}

2
src/mainboard/google/veyron_jerry/bootblock.c
View File

@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
/* spi0 for chrome ec */
write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);

2
src/mainboard/google/veyron_mighty/bootblock.c
View File

@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
/* spi0 for chrome ec */
write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);

2
src/mainboard/google/veyron_pinky/bootblock.c
View File

@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
/* spi0 for chrome ec */
write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);

2
src/mainboard/google/veyron_rialto/bootblock.c
View File

@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
setup_chromeos_gpios();
}

2
src/mainboard/google/veyron_speedy/bootblock.c
View File

@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
/* spi0 for chrome ec */
write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);