soc/intel/common: Add method to modify GPIO community PM config
This patch adds CGPM, a helper method to configure GPIO power management bits that are part of miscellaneous config. This is needed for configuration of these bits on S0ix entry and exit. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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/*
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* Configure GPIO Power Management bits
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*
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* Arg0: GPIO community (0-5)
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* Arg1: PM bits in MISCCFG
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*/
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Method (CGPM, 2, Serialized)
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{
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Local0 = GPID (Arg0)
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If (Local0 != 0) {
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/* Mask off current PM bits */
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PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG)
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/* Mask in requested bits */
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PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG)
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}
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}
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