soc/amd: Show SPI settings in bootblock

BUG=b:194919326
TEST=See SPI settings in bootblock

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

src/soc/amd/cezanne/early_fch.c

@@ -73,6 +73,7 @@ void fch_early_init(void)
 	pm_set_power_failure_state();
 	fch_print_pmxc0_status();
 	i2c_soc_early_init();
+	show_spi_speeds_and_modes();
 
 	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
 		lpc_disable_spi_rom_sharing();

src/soc/amd/picasso/early_fch.c

@@ -75,6 +75,7 @@ void fch_early_init(void)
 	pm_set_power_failure_state();
 	fch_print_pmxc0_status();
 	i2c_soc_early_init();
+	show_spi_speeds_and_modes();
 
 	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
 		lpc_disable_spi_rom_sharing();

src/soc/amd/stoneyridge/southbridge.c

@@ -357,6 +357,7 @@ void bootblock_fch_init(void)
 {
 	pm_set_power_failure_state();
 	fch_print_pmxc0_status();
+	show_spi_speeds_and_modes();
 }
 
 static void fch_init_acpi_ports(void)