Commit graph

1455 commits

Author SHA1 Message Date
Alexander Goncharov
893c3ae892 tree: Drop repeated words
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07 04:37:31 +00:00
Elyes Haouas
ced8fe0cb6 vc/amd/pi: Fix "No such file or directory"
Fix:
cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-05 00:57:27 +00:00
Bora Guvendik
c9f7e115fd vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshake
Expose DisableDynamicTccoldHandshake in header so that
coreboot can disable it.

BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=Boot to OS, check UPD value in debug FSP build.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0d953f37a2f0dac58fd339e3fe0dc847d5e6d892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72693
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03 19:02:07 +00:00
Patrick Rudolph
2a72e5d269 vendorcode: Add VariableFormat.h
Add the EDK2 variable format header in order to access the SPI flash
variable store.

https://github.com/tianocore/edk2/blob/edk2-stable202005/MdeModulePkg/Include/Guid/VariableFormat.h
Commit Hash: 9d510e61fceee7b92955ef9a3c20343752d8ce3f

Change-Id: Ibe44925555a7d1d2361dd48c0325b840bd68e0ca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61959
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31 16:45:29 +00:00
Jonathan Zhang
9355bc0919 vendorcode/intel/fsp/fsp2_0: add SPR-SP FSP header files
Intel Sapphire Rapids Scalable Processor was product launched
on Jan. 10, 2023.

Add the FSP/HOB header files corresponding to 2022 ww43 git tag
EGLSTRM.0.RPB.0090.D.03.

Change-Id: I818da37c10f40045d98a9f73e82034c3fe6459e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71948
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-29 18:43:25 +00:00
Kulkarni, Srinivas
6f37788ba5 vc/intel/fsp/mtl: Update header files from 2431_80 to 2473_86
Update header files for FSP for Meteor Lake platform to
version 2473_86, previous version being 2431_80.

FSPM:
1. Removed deprecated UPD PcieMultipleSegmentEnabled
2. Address offset changes

FSPS:
1. Removed deprecated UPD ForcMebxSyncUp
2. Address offset changes

BUG=b:261150757

Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.corp-partner.google.com>
Change-Id: Ie396ad7ef4da2d1c52d37477bbb0815d2d650841
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2023-01-24 07:40:40 +00:00
Paul Menzel
e88bf30d12 vc/siemens/hwilib: Use 3rd person singular in comment
Change-Id: I1d9d123d2a29178541ab24c70ba529f6bfa2b6c8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-18 22:07:07 +00:00
Werner Zeh
fcff39f0ea vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'
The parameter 'maxlen' can be a bit confusing as it actually is
referring to the size of the destination memory block where the
requested parameter is stored to. Rename it to 'dstsize' and change
the type to size_t to be more clear here.

In addition, add a comment line for this parameter in the description
of the function 'hwilib_get_field()'.

This patch has no impact to the generated binary (checked with timeless
build).

Change-Id: I572dc0f3ff3d0c177d608332a88991396b82c2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72045
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-01-18 22:06:35 +00:00
Werner Zeh
9a8e119110 vc/siemens/hwilib: Fix coding style
As per the code style there is no space before the opening brace of a
function declaration. Delete the space in hwilib.c and hwilib.h.

Change-Id: Ie122ccd2dbae97f595463a097826d3415718a8bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72044
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 22:03:01 +00:00
Elyes Haouas
24769421cd treewide: Fix old-style declarations
Replace old style declaration "const static" with "static const".
This to enable "Wold-style-declaration" command option.

Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-17 04:23:49 +00:00
Karthikeyan Ramasubramanian
ef1297689d soc/amd/mendocino: PSP_INCLUDES_HSP
Select HSP config to indicate that the SoC includes Hardware Security
Processor. This will allow PSP verstage to get and report the HSP state.

BUG=None
TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim.  Verify
that HSP is reported during the boot sequence.

Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15 02:27:11 +00:00
Karthikeyan Ramasubramanian
8420ccc6e9 vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure State
Add an SVC call to get the state of Hardware Security Processor (HSP) in
AMD SoCs. This SVC call will be used from PSP verstage to get and
report HSP state.

BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state
is read and reported in the firmware logs.

Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15 02:22:48 +00:00
Bora Guvendik
e8d4baca77 vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3503.00
The headers added are generated as per FSP v3503.00

BUG=b:261159242
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Cq-Depend: chrome-internal:5318308, chrome-internal:5318129
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I050c0f81dce1cfc5ef64406e75d9823352564836
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71758
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2023-01-13 23:42:27 +00:00
Elyes Haouas
4d616e372f vc/siemens/hwilib/Makefile.inc: Fix "No such file or directory" error
Fix:
cc1: error: src/vendorcode/siemens/hwilib: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I0e805ead90dddbee3ba3577d119e465f669231ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-13 16:49:18 +00:00
Elyes Haouas
977c807418 vc/eltan/security/Makefile.inc: Remove path to non-existent directory
Fix:
cc1: error: ../../src/vendorcode/eltan/security/include: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71298
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12 05:09:29 +00:00
Martin Roth
20646cdbe8 soc/amd: Change Morgana codename to Phoenix
Now that the next generation of APUs is officially announced, we can
unmask morgana.

The chip formerly known as Morgana is actually Phoenix.

Surprise!

This patch just changes the name across the entire codebase.

Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 03:13:17 +00:00
Derek Huang
da3812208e chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
When AP boots up after Cr50 firmware update and reboot, AP finds
that Cr50 reset is required for Cr50 to pick the new firmware so
it trigger Cr50 reset and power off the system, AP expects system
will power on automatically after Cr50 reset. However this is not
the case for Chromebox, Chromebox EC set AP_IDLE flag when system
is shutting down, when AP_IDLE flag is set in EC, the system stays
at S5/G3 and wait for power button presssend. It cause an issue in
factory that the operator needs to press power button to power on
the DUT after Cr50 firmware update.

This patch sends EC command to direct EC to clear AP_IDLE flag
after AP shutdown so AP can boot up when Cr50 reset.

BUG=b:261119366
BRANCH=firmware-brya-14505.B
TEST=DUT boots up after Cr50 firmware update in factory test flow

Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10 09:33:47 +00:00
Martin Roth
fbd13a84cf vc/google: Add and use POST_CODE_CLEAR definition
The CR50 code clears the post code value.  Add this as a #define.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-07 03:31:41 +00:00
Chris.Wang
ad12b4f440 soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization
Add the UPD dxio_tx_vboost_enable for PCIe optimization.
It will impact the PCIe signal integrity, need to double-confirm
the SI result after enabling this setting.

BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
     the FSP log.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 07:15:10 +00:00
Elyes Haouas
b3a28c3a66 vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
Fix:
    CC         romstage/mainboard/amd/pademelon/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]

    CC         romstage/mainboard/amd/gardenia/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]

    CC         romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]

    CC         romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-03 18:09:50 +00:00
Felix Singer
9df60d36b2 tree/acpi: Replace constant "Zero" with actual number
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27 09:06:47 +00:00
Eric Lai
8cb2f185d1 vc/google/chromeos: use fw_config field to return sar filename
Use fw_config field to return sar filename instead of fw_config probe.
Return filename unconditionly because the sar_id must be valid in
CBI. If invalid sar_id, the file won't exist in CBFS by design.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24 05:50:13 +00:00
Karthikeyan Ramasubramanian
7b49d1b198 vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUS
Add an SVC command to get the previous boot status. If there is any
pre-x86 boot failure in the previous boot cycle, PSP stores it in warm
reset persistent register and triggers a warm reset. PSP verstage on the
subsequent boot gets the previous boot status and reports any failure to
the vboot before a FW slot is selected.

BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure
scenario by corrupting certain firmware blobs and observe that PSP
reports the failure boot status. On a normal boot, observed that PSP
reports successful boot.

Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:36:25 +00:00
Subrata Banik
6ed431589b vc/intel/fsp/mtl: Update header files from 2404_00 to 2431_80
Update header files for FSP for Meteor Lake platform to
version 2431_80, previous version being 2404_00.

FSPM:
1. Address offset changes

FSPS:
1. Address offset changes

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14 06:47:47 +00:00
Felix Singer
18af706d50 vc/google/chromeos/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I8b2d97063ba199274c1072ba3a12613162a17ef1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:46:20 +00:00
Elyes Haouas
3cd89a003b vc/eltan/security/mboot/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ie2c4a6c2bb55af56cb6e0b013b1a2ed9baa787ef
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70460
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-13 15:19:58 +00:00
Felix Held
d3690ee19c vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy config
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-12 15:19:45 +00:00
Saurabh Mishra
f339b63b02 vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.h
Changes include:
- FirmwareVersionInfoHob.h is removed to use new header file
  FirmwareVersionInfo.h.

BUG=b:260183604
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-12 13:50:04 +00:00
Saurabh Mishra
997e9f74a1 vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.h
Changes include:
- Add header file FirmwareVersionInfo.h

BUG=b:260183604
BRANCH=None
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: Ib5c843bb0dccd5db92f74148df3a17037988392c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69882
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:49:31 +00:00
Elyes Haouas
3d1b2db1af vc/mediatek/mt8195/Makefile.inc: Remove path to non-existent folder
The directory src/vendorcode/mediatek/mt8195/dramc/include never
existed, and was added in commit b0b8dc37
(vendor/mediatek: Add MT8195 dram initialization code).
Found using 'Wmissing-include-dirs' command option.


Change-Id: Iec349e816a1b646f1ea5fa1db13e05a78ffe1af8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70464
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:30:26 +00:00
Felix Held
bd9ab06808 vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy config
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this. Also make sure that the address of the lcl_usb_phy
struct is located below the 4GB boundary, so that the truncation to 32
bits won't result in pointing to a different memory location than
intended. In this error case, which I don't expect to happen, print an
error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its
default values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:26:03 +00:00
Shaik Shahina
ba3b2f8fd8 vc/intel/fsp: Update ADL N FSP headers from v3343.04 to v3343.05
Update generated FSP headers for Alder Lake N from v3343.04 to v3343.05.

Changes include:
-FspsUpd.h : Update UfsEnable UPD description in comments

BUG=b:228110908
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.

Change-Id: Ieff33df2d2b0884a9788e05e06da5bdae1be08de
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70446
Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 20:45:46 +00:00
Elyes Haouas
1d99076c7d vc/mediatek/mt8192/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: I79457d8548700eeb534419f8e41990fad05edb68
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70398
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 17:08:32 +00:00
Elyes Haouas
4f3251ed16 vc/eltan/security/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ia6f72acf0ae90c98ccf1fbbeedd7fbf5f194b4cc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70385
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 16:59:44 +00:00
Felix Held
e1f6db512f vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configuration
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08 18:01:38 +00:00
Felix Held
7969a5c1b4 vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy config
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08 17:57:41 +00:00
Elyes Haouas
33e9e44a17 vc/cavium/bdk/libbdk-arch/bdk-numa.c: Fix old-style function definition
Change-Id: Ia56f813933143ef69c97f1b7643693c6eade6abe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-06 16:18:59 +00:00
Bora Guvendik
a6f6e6a592 vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.12
The headers added are generated as per FSP v3361.12

BUG=b:261159242
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: Id7986017e1256627027a45325238bf29e0c00cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-05 21:10:26 +00:00
Saurabh Mishra
060492ecd2 vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.h
Fix compilation issue due to enum macro redefinition by safeguarding
definitions with DISPLAY_FSP_VERSION_INFO_2 in SoC Kconfig.

Back-ported from commit f7e8adac7b ("edk2-stable202005: Update
MdePkg/Include/IndustryStandard/SmBios.h") to fix compilation issue due
to enum macro redefinition.

BUG=b:260183604
TEST=Verify MTL Rex0 build with the patch
and verify the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2022-11-26 23:45:26 +00:00
Fred Reitberger
2b9ee5d79e vc/amd/fsp/glinda/platform_descriptors.h: Update for glinda
Update definitions on glinda used by birman.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I03065011581489b5345c16e225edc341e1d7811c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19 02:47:48 +00:00
Fred Reitberger
4875a1f054 vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana
Update definitions to match morgana FSP.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic893526789c05a298965702114d4a814466a5742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19 02:46:49 +00:00
vjadeja-intel
0ddeaedbe8 vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00
Update header files for FSP for Meteor Lake platform to
version 2404_00, previous version being 2364_00.

FSPM:
1. Address offset changes
2. Rename `PlatformDebugConsent` to `PlatformDebugOption`

FSPS:
1. Address offset changes

Additionally, incorporate the UPD name change for MTL romstage.

BUG=b:255481471
TEST=Able to build and boot Google, Rex to ChromeOS.

Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 00:01:56 +00:00
Sergii Dmytruk
7221a6cfc5 security/tpm: improve tlcl_extend() signature
Until now tcg-2.0/tss.c was just assuming certain buffer size and
hash algorithm. Change it to accept digest type, which the call sites
know.

Also drop `uint8_t *out_digest` parameter which was always `NULL`
and was handled only by tcg-1.2 code.

Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68745
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-11-12 23:16:07 +00:00
Elyes Haouas
898176a24c treewide: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 18:00:16 +00:00
Martin Roth
e440403683 vc/amd/fsp/mendocino: Update FSP UPD signatures to MNDCNO
The FSPM and FSPS UPD signatures hadn't been updated from their cezanne
origins.  Change them to MNDCNO_M/S.

BUG=b:240573135
TEST=Build & boot, see new signature in boot log.

Change-Id: I9e4fcf7a9bf802aaba88f3dccf6da064c5686e96
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-11-11 00:39:20 +00:00
Jonathan Zhang
fe17a7d4d4 soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.

Re-define in the common code.

Update coreboot code to use FSP_X_CONFIG consistently.

Tested=On OCP Delta Lake, boot up OS successfully.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>

Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-08 22:55:20 +00:00
Selma Bensaid
67ce1f251a vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07
The headers added are generated as per FSP v3361.07

In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.

BUG=b:254054169
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-07 20:45:00 +00:00
Arthur Heymans
7d6bf83afc vendorcode/amd/ccx_cppc_data.h: Fix header guard
Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69230
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 14:21:30 +00:00
Arthur Heymans
03a6ccd20d sb/amd: Remove dropped platforms
This code is now unused by any platform.

Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:59:17 +00:00
Arthur Heymans
81a4fefce2 cpu/amd/agesa: Remove leftover code
Now that all agesa CPUs are removed this code is unused.

Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:58:48 +00:00