Commit Graph

29828 Commits

Author SHA1 Message Date
Christian Walter 04f995150f configs: Add test-build for up squared with vboot enabled
It would be useful if we have at least one "new" board on which we
actually built vboot, in order to notice if something breaks.

Change-Id: I16c7867e3f0f4e1f2e6ae3918c30789e39881b85
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-29 18:26:20 +00:00
Pavel Sayekat 9429b70f91 util/inteltool: Add H110 GPIO support
Change-Id: I0ce22da3d201c2443bb5a7fcfd779c2c6ee71577
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34602
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 18:06:13 +00:00
Christian Walter 90cf4bb02a Revert "src/security/vboot: Add option to skip display init with vboot 2.0"
This reverts commit 598af2e2c2.

Reason for revert: This commit breaks every board with VBOOT enabled
if the platform is apollolake, broadwell, skylake, baswell, baytrails
or icelake. The reason is, that the SoC selects
VBOOT_MUST_REQUEST_DISPLAY by default, and this has a dependency now
on VBOOT_MAY_SKIP_DISPLAY_INIT. This will only be auto-selected if
it is a CHROMEOS platform.

Change-Id: I3872d9aa993326ded135d8a5d950d5b1b1eddf34
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34308
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 17:21:09 +00:00
Pavel Sayekat 98d5a86ec0 src/superio/nuvoton: Add support for NCT5539D
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015).

Change-Id: I7e979bde53ce3dac1a4f74e7e51a3c6a0149051c
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33842
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 17:02:12 +00:00
Christian Walter 931e991325 Revert "soc/intel/common: Set controller state to active in uart init"
This reverts commit 46445155ea.

Reason for revert: Breaks coreboot. Either no UART working or the
complete boot process stops.

Platform: Intel Apollolake, tested on Up Squared

Change-Id: If581f42e423caa76deb4ecf67296a7c2f1f7705d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-29 11:20:18 +00:00
Jacob Garber 53b4b2850c soc/qualcomm/qcs405: Handle invalid QUP and BLSP
Print an error message and return if an invalid QUP or BLSP is
encountered. This prevents a possible null pointer dereference
of spi_clk.

Change-Id: I374e15ce899c651df9c2d3e0f1ec646e33d4bdb2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401086
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29 06:09:17 +00:00
Jacob Garber 767c4b2899 soc/intel/baytrail: Prevent unintended sign extensions
Consider the following assignment:

    u64 = s32

For positive values this is fine, but if the s32 is negative, it will be
sign-extended in the conversion to a very large unsigned integer. This
manifests itself in two ways in the following code:

First, gpu_pipe{a,b}_port_select are defined as int, and can have the
values 1 or 2. In the case when they have the value 2, the shift 2 << 30
will be a negative number, making it susceptible to the sign-extension
problem above. Change these variables to something more reasonable like
a uint8_t, which is unsigned.

Second, in any bit shift, any variable with width less than an int will
be implicitly promoted to an int before performing the bit shift.
For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its
highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become
negative, again introducing the above problem. To prevent this, cast all
smaller variables to a u32 before the shift, which will prevent the
implicit promotions and sign extensions.

Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 06:08:21 +00:00
Raul E Rangel 5592cfd5b3 Makefile: Don't create build directory for additional targets
BUG=b:112267918
TEST=Ran make help and verified build directory is no longer created

Change-Id: I4bb066b5c3b3d9a7bb19291ef928042b90f10440
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29 06:03:09 +00:00
Raul E Rangel 135bc3652e src/mainboard/{cavium,sifive}: Use $(obj) instead of build
The build directory might not exist in the src dir.

BUG=b:112267918
TEST=make what-jenkins-does

Change-Id: I2d4fa6cc455592f92070796cd065cd66646d5ba9
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29 06:02:37 +00:00
Jacob Garber 693c55c545 soc/nvidia/tegra124: Assert divisor is non-zero
The logic for the calculation of plld.m is rather complicated, so do a
sanity check that it is non-zero before doing the division.

Change-Id: I60f49b8eed47a3de86713304bde7a4d3f3d935dd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1260981
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-29 06:01:42 +00:00
Jacob Garber 321daa86ef vc/cavium/bdk/libdram: Print unknown voltages
volt_str is used to print information about the RAM configuration
in report_common_dimm(), so let's print out "unknown voltage" if the
voltage isn't recognized rather than a garbage value.

Change-Id: I8e85917fd682e166172fbf10597bde4a8a11dfc7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1393958, 1393982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-29 06:01:16 +00:00
Iru Cai 336420348e haswell: reinitialize EHCI debug hardware after raminit
Tested on Lenovo ThinkPad T440p.

Change-Id: I54b0c9dbb64819f0f502783b632470d27ed0b2b1
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34358
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 05:59:52 +00:00
Marshall Dawson b85ddc5d44 util/amdfwtool: Correct fletcher32 algorithm
Change the fletcher32 checksum calculation to match PSP and AGESA
implementations.

The symptom of the failure has only been noted in Picasso's BIOS
Directory Table, when a BIOS binary image of different sizes were
passed to amdfwtool.  The PSP halts the boot process with the bad
BDT checksum, and if allowed to continue, AGESA asserts later due
to a failed BDT verification.

This version has been verified to produce the same result as found
at https://en.wikipedia.org/wiki/Fletcher%27s_checksum.

TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom
     is unchanged.

Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-29 05:58:08 +00:00
Wisley Chen dffa781558 mb/google/octopus: Add keyboard backlight support
Dorp device support keyboard backlight, so enable it.

BUG=b:138413969
BRANCH=octopus
TEST=emerge-octopus coreboot

Change-Id: If0c7b22b4be2a5d5216404a6944ac887883e9a47
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2019-07-29 02:59:23 +00:00
Aamir Bohra 47ea45190b soc/intel/cannonlake: Correct the data type of serial_io_dev
Change-Id: Id974a4bb84b7d5caddece04f93bf4e830d15b576
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34466
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 02:06:36 +00:00
Nico Huber eaeb0b7892 sb/intel/common/spi: Fix opmenu setup
Remove a spurious reference: the `optype` field is already the pointer
we want.

Change-Id: I65eb3a519db9037c84750c5d40e3f19a1e360361
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-28 17:54:02 +00:00
Patrick Rudolph 1a64194307 riscv: Remove unused headers
Change-Id: I4cd03e043e1bc2795b98d6ec2f88efa5b50d872b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-28 16:34:11 +00:00
Patrick Rudolph bd4bcab8ad lib: Rewrite qemu-armv7 ramdetect
* Move armv7 RAM dection to a common place
* Enable it for all emulated platforms
* Use 32bit probe values and restore memory even on failure
* Use the new logic on the following boards:
** qemu-armv7
** qemu-riscv

Tested on qemu-system-riscv:
Fixes kernel panic due to wrong memory limits reported.

Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-28 11:31:42 +00:00
Martin Roth 57e257d987 util/abuild: Add asserts flag to getopts
We recently added the --asserts option to set asserts as fatal in abuild
but didn't add the flag to getopts, so it gets rejected as an invalid
argument.

Change-Id: Ic70e9a2bec039955cf62c175875598773ade2d3d
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-28 09:58:20 +00:00
Frans Hendriks 6a27e76696 mainboard/facebook/fbg1701: Add VBT binary
Add VBT 8.0.1038 binary.

Panel #10 is modified to support the 1200x1920 LCD panel.
This panel is configured as default.

LCD and HDMI are working fine.

BUG=N/A
TEST=booting Facebook FBG1701

Change-Id: If327e4e071df61b02fcec45213c2b700320ef269
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-28 09:36:26 +00:00
Patrick Rudolph b5871e5ccf 3rdparty/opensbi: Bump version
Use latest OpenSBI that include support for dynamic firmware loader.

That allows us to use OpenSBI similar to BL31 on aarch64:
* coreboot loads the payload
* coreboot loads OpenSBI ELF right before payload handoff
* OpenSBI does platform lockdown and provides runtime services
* OpenSBI hands control to already loaded payload

The uncompressed compiled OpenSBI code is about 41KiB.

Required to boot GNU/Linux on qemu-riscv as some instructions needs to be
emulated by SBI.

Change-Id: If7ed706bc54a75fb583a8aa46fdd61ae7d18c546
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-28 09:35:21 +00:00
Patrick Rudolph 403f433238 sb/intel/bd82x6x: Add support to disable xHCI
Set FD bit if xHCI is disabled in devicetree.

Change-Id: I3d08ded10daea6d86857ebbbf3f8dcc85ebe9df4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-26 21:16:13 +00:00
Richard Spiegel ae5b3671b3 superio/fintek: Add f81803A
Add f81803A plus the capability to control the fan with any fintek SIO.
This will be done through a common API, though currently only F81803A will
have it implemented.

BUG=none.
TEST=Tested later with padmelon board.

Change-Id: I3d336e76bccc38452b1b1aefef5d4a4f7ee129a8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-26 20:33:16 +00:00
Arthur Heymans 150a61e103 arch/ppc64: Make PPC64 stages select ARCH_PPC64
Also don't define the default as this result in spurious lines in the
.config.

This also cleans up an unused Kconfig file.

In the generated config.h CPU_QEMU_POWER8 is gone as expected and
ARCH_RAMSTAGE_PPC64 moves a few lines, but the value stays the same.

Change-Id: I70b64e49e1ce07b8f30d9bbc493272bdfb3bb0bf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-26 13:00:48 +00:00
Angel Pons ef3caf053e soc/intel/baytrail/Makefile.inc: Sort entries
Change-Id: Ic35a901c8272928a0389b38a74f4eac74977a080
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-26 13:00:11 +00:00
Erin Lo bbeed7ac72 soc/mediatek/mt8183: Init SSPM
Load SSPM firmware and boot up SSPM.

BUG=b:80501386
BRANCH=none
Test=We can see "SSPM is alive" in ATF stage if SSPM enabled and ipi success

Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31835
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26 12:59:28 +00:00
Jacob Garber 83369fa6f4 soc/nvidia/tegra124: Correct bitwise operators
We are treating reg_val like a bit mask, so use bitwise or instead of
boolean or, and use |= to enable certain bits instead of overwriting the
whole variable.

Change-Id: Ia8c0ea5a58e25b3b58ed82caba20f8e49a30fb68
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1287070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-26 12:58:57 +00:00
Tim Wawrzynczak 532f205a05 mb/google/hatch/helios: Update GPIO and device tree
Based on updated schematics, change polarity of USI_INT, and add
the reset and enable GPIOs to the touchscreen ACPI node.  The stop
GPIO can't be used with the current implementation of _ON, as the
way it's wired will cause power sequencing to fail.

BUG=b:137133194, b:138240502
BRANCH=none
TEST=Compiles, don't have next board rev to test with

Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-26 12:58:44 +00:00
Patrick Georgi 19d04388a3 lib: add string.c to verstage
Change-Id: I5aa3bb2c72dcf127d418c989f6b63c9b1f412f08
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-26 11:09:05 +00:00
Patrick Georgi 99f0e0c4dc util/testing: Allow adding abuild options to what-jenkins-does
JENKINS_ABUILD_OPT is passed in abuild's command line

Change-Id: I5e7fbb77a3c6592a4414a6c1e3f7556c7e3a824c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:07:01 +00:00
Patrick Georgi 3a0cad30f2 util/abuild: Add --asserts flag
This enables fatal asserts, which can be useful to get better
diagnostics by the build tools (both compilers and static analysis.)

Change-Id: I1e1653f465fe1f545878d6eec83b8645dc17d9cb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:06:29 +00:00
Patrick Georgi c199973f78 util/testing: Factor out abuild options in what-jenkins-does
The abuild command line can vary a lot depending on options and the line
became unwieldy (plus, it's on two lines because we run abuild twice),
so factor it out into a variable.

Change-Id: I102756fb95c93f542d534610bf9737a13ac1ad62
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:06:22 +00:00
Patrick Georgi ccab651ded libpayload/serial/qcs405: Mark uart console as such
depthcharge prefers knowing where its input comes from

BUG=b:137378326
BRANCH=none
TEST=ctrl-d / enter to enter dev-mode works now.

Change-Id: I74b5be18c3583be17c73950ced93fad883690090
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-26 08:41:38 +00:00
Johanna Schander db7a3ae863 src/device/oprom: Fix bootsplash display code for optionroms
So far the bootsplash is only correctly rendered if the framebuffer is
set up as 1024x768@16.
Different resolutions did not show anything, differnent depth resulted
in the distorted images.

This commit removes this limit by using the actual framebuffer resolutions
and combines the code for x86 and yabel.

For the moment the bootsplash is still limited to VGA-OptionROM
framebuffer init.

It was tested in 1280x1024@32 on the wip razer blade stealth using the
intel vgabios.

Change-Id: I5ab7b8a0f28badaa16e25dbe807158870d06e26a
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34537
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26 08:40:23 +00:00
Kyösti Mälkki a31cd21c3a oprom/yabel: Fix comment to fix the build
Old comment did not match the pattern required
to not flag the fall-through as an error.

Change-Id: I2afaca969c295a5dc4389dad0ce898c87bb841a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-26 08:39:31 +00:00
Nico Huber cf96c2a4f1 payloads/external/Yabits: Pass XGCCPATH
Pass `XGCCPATH` instead of individual programs as that is what the
Makefile expects.

Change-Id: I3267ec5259e9d37b2f3b0b8c126d173fc8b5a3ca
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25 20:22:00 +00:00
Nico Huber 517ed8b0e4 xcompile: Store XGCCPATH
It can be useful to pass along to external projects, e.g. payloads.

Change-Id: I61c7bb162e2737a562cbef08b32ebbafd9cf1cb0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25 20:18:52 +00:00
Martin Roth d70f5fae1c crossgcc: Add nasm to toolchain
Tianocore payload uses nasm.  Supply it in the coreboot toolchain
instead of relying on system version.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33024
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 19:05:22 +00:00
Elyes HAOUAS 1662c0bbfe crossgcc: Upgrade CMake to 3.15.0
Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html

Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33053
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:41:23 +00:00
Elyes HAOUAS 43e9bd6b9c crossgcc: Upgrade acpica to version 20190703
Changes: https://acpica.org/node/171

Change-Id: I3883718623e4a23a901a446f738a9e8c988d8433
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25 18:40:56 +00:00
Elyes HAOUAS 1e9473cc25 crossgcc: Upgrade Expat to version 2.2.7
Change-Id: If3611494228a9228b0b323038ba1e884a1bde10f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33825
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:33:01 +00:00
Elyes HAOUAS 7e3eab2c13 crossgcc: Upgrade Python to version 3.7.4
Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32077
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:32:39 +00:00
Elyes HAOUAS 31270646ba crossgcc: Upgrade GDB to version 8.3
Change-Id: I7a85ad171fa259e0dcb0019941d735ef41511737
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32754
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:28:00 +00:00
Elyes HAOUAS 77f778c0c3 ec/google/wilco: Hide wilco symbols when unused
This cleans up .config file from unused wilco symbols.

Change-Id: I813d3fe57b97e2c1ba67e1e3674de256c2529029
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34539
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 16:46:17 +00:00
Kyösti Mälkki c9c80c6907 soc/intel/fsp_broadwell_de: Fix use of config_of()
Change-Id: I96d423720fbe67c067373436ad250edf37939e99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25 16:45:12 +00:00
Kyösti Mälkki b28658995d soc/intel: Guard remaining SA_DEV_ROOT definition
Prevent implicit cast to pointers.

The compiler doesn't warn about the conversion from
integer to pointer without a cast, because SA_DEV_ROOT
is literally '0' and there seems to be an exception
for that conversion.

Change-Id: I64fc156e3b9f578414ad03a00edb7cf3e33205c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-25 16:43:13 +00:00
Kyösti Mälkki 326edeb59c soc/intel/broadwell: Fix case of SA_DEV_ROOT
Commit 71756c2 soc/intel: Expand SA_DEV_ROOT for ramstage
removed SA_DEV_ROOT expanding to device pointer. We missed
the case here, use __SIMPLE_DEVICE__ instead for the file.

Change-Id: I4331298837afa3b8c8321da610f99f8f5fa54737
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-25 16:42:26 +00:00
Matt DeVillier ea24414605 mb/purism/librem_skl: use SOC_INTEL_COMMON_BLOCK_HDA_VERB
Remove old hda_verb.c code copied from intel/kblrvp7, as it's
been superseded by the common block HDA implementation.

Fixes a null pointer error preventing the HDA codecs from being
initialized, as found in Coverity CID 1403651.

Test: build/boot Librem 13v2, verify functional audio

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I2fd5363aad027f215f93964bc6a85f00fea86c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34531
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 16:41:32 +00:00
Elyes HAOUAS cd92979d44 mb/getac/p470: Remove unneeded whitespaces
Change-Id: I8e36dc1553faa618aa852c06861029b4c0bdb27a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-25 16:08:21 +00:00
Elyes HAOUAS 17b1a166a3 soc/{qualcomm,rockchip}: Use 'include <stdlib.h>' when appropriate
Also including <types.h>, is supposed to provide stdint and stddef.

Change-Id: Iab605f6be4a48c10fa5aae7a1222520149ad1392
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25 16:06:54 +00:00