Commit Graph

46849 Commits

Author SHA1 Message Date
Wisley Chen dc27d807ba driver/intel/usb4/retimer: Change loglevel prefix
In usb4_retimer_fill_ssdt(), it search all dpf ports and shows message
in not support dpf ports.
It's not error and changes the loglevel prefix to BIOS_INFO.

BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:44:10 +00:00
Wisley Chen 9006d8b746 soc/intel/alderlake/retimer: Change loglevel prefix
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to
BIOS_INFO instead.

BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:43:30 +00:00
Wisley Chen de7cac82d6 ec/google/chromeec: Change loglevel prefix
In most boards, it doesn't write OEM_NAME in CBI to override the
manufacturer name in the SMBIOS table. It' better use the "BIOS_INFO" than "BIOS_ERR"

BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:43:04 +00:00
Dtrain Hsu 29571e80b3 mb/google/brya/var/kinox: Modify 15W SOC power control setting
Modify 15W SOC default power settings for kinox.
- PL2 39W
- PL4 100W
- Psys_PL2 65W
- Psys_imax_ma 5000ma
- bj_volts_mv 20000mv

BUG=b:213417026, b:222599762
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 14:42:24 +00:00
Subrata Banik 2f1f5ecf8a soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC
This patch refactors the current P2SB common code driver to accommodate
the future SoC platform with provision of more than one P2SB IP in
disaggregated die architecture.

IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with
MTL, one more P2SB IP resides in IOE die along with SoC die. (PCH die is
renamed as SoC in MTL.)

P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c
is added only for PCH/SoC P2SB.

BUG=b:224325352
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-17 14:37:43 +00:00
Raihow Shi 9e4a38795c mb/google/brask/variants/moli: set eMMC pin in bootblock
1.Assert eMMC enable pin in bootblock
2.Deassert eMMC reset pin in bootblock

BUG=b:220821454

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:36:46 +00:00
Taniya Das 5fa28a5404 qualcomm/sc7280: Add mdp clock support to turbo in coreboot
This change supports the configuration and enablement of
mdp clock to vote for turbo and supports different display
panel resolutions and framerates.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62371
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 14:36:24 +00:00
Taniya Das af2c89c463 qualcomm/sc7280: Add display external clock support in coreboot
Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.

BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 14:36:07 +00:00
Eric Lai e93bce937e mb/google/nissa/var/nivviks: Set gpio override to board_0
Follow the latest schematic change, gpio will match the baseboard.
Return the current table as override.

BUG=b:223677877
TEST=audio is functional on board_0.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-17 14:35:48 +00:00
Matt DeVillier 23be41880c ec/chromeec/ec_smbios: Set system manufacturer for ChromeOS devices
Currently, many Linux drivers use DMI quirks to identify ChromeOS
devices and handle them accordingly: namely they look for the SMBIOS
system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be
coreboot. Historically this was consistently the case, but recent model
ChromeOS devices allow the OEM to set the mainboard manufacturer, which
is also the default system manufacturer. This breaks many DMI quirks,
notably ones used by SOF (sound open firmware) for audio.

To fix this, set the system manufactuer for ChromeOS devices to "Google"
for devices selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID, leaving the OEM
customization in place for the mainboard manufacturer. Since boards
selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID are the only ones overriding
the default mainboard manufacturer, they are the only ones which need
this correction.

Test: build/boot google/bloog with Linux 5.16, verify SOF drivers
correctly detect device as a Chromebook and load the appropriate
audio firmware.

Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62796
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 14:35:33 +00:00
Curtis Chen 3fc3e6c609 soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values
Add ADL-P MCH ID 4, 8, 9, 10 into this list.

BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:30:13 +00:00
Subrata Banik 73ad818bc9 soc/intel/common/block/cpu: Enable ROM caching in ramstage
Cache the BIOS region and extended BIOS region if the boot device is
memory mapped, which is mostly the case with Intel SoC platform.
Having the ROM region cached helped to improve the pre-boot time.

TEST=Able to boot redrix to Chrome OS without seeing any sluggishness.
Additionally verified on EHL board (from siemens), shows significant
savings in payload loading time as below:

Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:

upstream:
  90:starting to load payload                    1,072,459 (1,802)
 958:calling FspNotify(ReadyToBoot)              12,818,079 (11,745,619)

with this patch:
  90:starting to load payload                    1,072,663 (2,627)
 958:calling FspNotify(ReadyToBoot)              5,299,535 (4,226,871)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-17 06:02:04 +00:00
Subrata Banik 1f28c853de soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
This patch provides a way to cache `ext_bios` region for all stages to
save boot time.

TEST=Able to see the ext_bios region in MTRR snapshot when cached on
the Brya variants.

Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:

upstream:
  90:starting to load payload                    1,072,459 (1,802)
 958:calling FspNotify(ReadyToBoot)              12,818,079 (11,745,619)

with this patch:
  90:starting to load payload                    1,072,663 (2,627)
 958:calling FspNotify(ReadyToBoot)              5,299,535 (4,226,871)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-17 06:01:49 +00:00
Subrata Banik 242e2665d0 include/efi: Clean up efi_datatype.h file
This patch cleans up `efi_datatype.h` to allow other SoC and/or driver
code to use this file.

`PiPei.h` file only gets added from UDK2017 hence, the platform with the
older EDK2 base (prior to UDK2017) is unable to resolve this file
dependency.

This CL removed the `PiPei.h` header and only added the required header
file `PiPeiCis.h` for platforms with UDK base >= 2017.

BUG=b:200113959
TEST=Able to build Brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9177814fcf41e5950ace94050356f0273f765c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 06:00:54 +00:00
Eric Lai 6e3d42ab42 drivers/wifi/generic: Fix is_cnvi function
dev->ops = &wifi_cnvi_ops need is_cnvi be true. This cause the exclusive
statement so is_cnvi never be true in !DEVTREE_EARLY.

BUG=b:224317408
TEST=no assertion in coreboot.
[EMERG]  ASSERTION ERROR: file 'src/acpi/acpigen_pci.c', line 24

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I1ca6312ce164c43021686b483f6579164614cede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 04:57:43 +00:00
Ravi Kumar Bokka 4573ca42e6 soc/qualcomm/common: Add dram information to CBMEM table
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-03-16 23:08:05 +00:00
Felix Singer 944291d458 mb/hp/snb_ivb_laptops: Move selects from Kconfig.name to Kconfig
Move selects from Kconfig.name to Kconfig so that the configuration is
in one place and not distributed over two files.

Change-Id: I500f6422c1f8975de8b0bcc8b95cba2bcd4ebe27
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16 18:27:28 +00:00
Dtrain Hsu 335edc0f5d mb/google/brya/var/kinox: Enable PCIe-eMMC bridge
Enable PCIe-eMMC bridge for Kinox.

BUG=b:218786363, b:211176722
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:57:26 +00:00
Dtrain Hsu 60260a5ed6 mb/google/brya/var/kinox: Modify the DPTF/Fan parameters
Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters.

BUG=b:221180425, b:222020226, b:221182596
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:57:06 +00:00
Sridhar Siricilla 073da0cbae soc/intel/common: Retry MEI CSE DISABLE command
As per ME BWG, the patch retries MEI CSE DISABLE command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.

TEST=build and boot the Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:56:50 +00:00
Sridhar Siricilla 92bd71ff74 soc/intel/common: Retry END_OF_POST command
As per ME BWG, the patch retries END_OF_POST command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.

BUG=b:200251277
TEST=Verify EOP retry mechanism for brya board.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:56:34 +00:00
Jason Glenesk bddb16ba76 3rdparty/amd_blobs: advance submodule pointer
This adds the following commits:
 * a069321 cezanne: Update SMU firmware to 64.62.0
 * d8a51cb cezanne: Upgrade ABL to 0x22146070

Change-Id: I066252eda56b8b62db420cbcfc95c97875a3b6d1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-16 16:56:06 +00:00
Jianjun Wang 5111326c5c soc/mediatek: PCI: Remove global variable
Remove global variable and use 'pcidev_path_on_root()' to get the base
address of PCIe controller.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16 16:55:52 +00:00
Jianjun Wang c0808b6497 soc/mediatek: Add chip config for setting PCIe config
Add chip config for setting PCIe config.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16 16:55:26 +00:00
Raul E Rangel d59b3dd085 soc/amd/common/block: Add mainboard_handle_smi
The current SMM framework only allows the mainboard code to handle GPEs.
i.e., Events 0 - 23. This change allows the mainboard code to handle any
SMI events not handled by the SoC code. This will allow the mainboard
code to handle `SMITYPE_ESPI_SMI`.

BUG=b:222694093
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-16 16:33:32 +00:00
Felix Singer 589609c8e7 mb/hp/snb_ivb_laptops: Rename `BOARD_HP_SNB_IVB_LAPTOPS`
Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON`
to indicate and to make it clear that this option serves as base for
others.

Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with
`INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical.

Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16 15:55:18 +00:00
Felix Singer 339ca7f11a mb/hp/snb_ivb_laptops/Kconfig{,.name}: Reorder selects alphabetically
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and
coreboot.rom remains identical.

Change-Id: I54367c7c663ad288ccdcbd4e7289546489a68f30
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16 15:54:35 +00:00
Mark Hsieh f25e42c4f4 mb/google/brya: set GPP_D0 to GPO
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is
directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP
firmware successfully.

BUG=b:222188263, b:223906569
TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint
Firmware Test.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-16 04:10:59 +00:00
Ravi Kumar Bokka 42fcb2a8f4 libpayload: Parse DDR Information using coreboot tables
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-16 01:21:44 +00:00
Jes Klinke 19baa9d51e i2c: Add configurable I2C transfer timeout
This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US,
which controls how long to wait for an I2C devices to
produce/accept all the data bytes in a single transfer.
(The device can delay transfer by stretching the clock of
the ack bit.)

The default value of this new setting is 500ms.  Existing
code had timeouts anywhere from tens of milliseconds to a
full second beween various drivers.  Drivers can still have
their own shorter timeouts for setup/communication with the
I2C host controller (as opposed to transactions with I2C
devices on the bus.)

In general, the timeout is not meant to be reached except in
situations where there is already serious problem with the
boot, and serves to make sure that some useful diagnostic
output is produced on the console.

Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-15 22:06:27 +00:00
Subrata Banik ca82e6161a util/ifdtool: Add Meteor Lake platform support under IFDv2
BUG=b:224325352
TEST=Able to build ifdtool.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3564efa27d0271286435284e745458aada987008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-15 19:22:49 +00:00
Michael Niewöhner d3b85223fd soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.

Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15 19:22:19 +00:00
Sean Rhodes bba7e601a8 intel/common/block: Add APL and GLK PCI IDs for HDA
Add PCI ID's for APL/GLK so they can use HDA.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-15 19:21:46 +00:00
Kevin Chiu 29919f81fa mb/google/guybrush/var/nipperkin: update APU STT setting
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     update the thermal setting value by measurement and
     pass the thermal performance test

Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-15 19:19:36 +00:00
Frank Wu bd0ba39172 mb/google/brya/var/banshee: Add camera privacy setting
Using the GPP_F19 as privacy switch for camera in banshee.

BUG=b:223712143, b:216110896
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-15 19:19:21 +00:00
Werner Zeh 9b565de3a0 lib/spd: Do not print part number if it is not available
If the DRAM part number is not available in the SPD data (meaning filled
with 0x00) do not print it in the log.

Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15 19:18:54 +00:00
Rex-BC Chen 69e3cab7f9 soc/mediatek/mt8186: change pmic hwcid from warning to info
The pmic hwcid dumping should not be a warning, so we modify it to info.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15 19:17:48 +00:00
Rex-BC Chen 129b8ae551 soc/mediatek/common: Add halt() after triggering wdt reset
It's more reasonable to halt when we trigger watchdog reset because
the whole system should be reset afterwards.

BUG=b:222217317
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15 19:17:12 +00:00
MAULIK V VAGHELA a4cdb5b381 mb/google/brya: Disable C1-state auto demotion for Brya & Brask
C1-state auto demotion feature allows hardware to determine C1-state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.

Also, disabling this feature results in 110 mW power savings during
video playback.

Note that C1state Autodemotion feature is not applicable for ADL-P SoC.
Hence recommendation is to keep it disabled.

BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of c1-state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.

Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-15 18:11:37 +00:00
MAULIK V VAGHELA 99356386a6 soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.

This patch hooks up this parameter to devicetree

BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Check code compiles and correct value has been passed to FSP.

Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15 18:11:16 +00:00
MAULIK V VAGHELA 215a97ee1c soc/intel/adl/chip.h: Convert all camel case variables to snake case
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.

By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.

During renaming process, this patch also removes unused variables
listed below:
-> SataEnable   // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used

Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.

BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.

Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15 18:10:41 +00:00
Eloy Degen 6207a3967e Documentation/tutorial/part1.md: Add Fedora package `patch`
It is necessary to build crossgcc.

Change-Id: I32f6507b4d8346bf94aaccd3eef4f22697c33965
Signed-off-by: Eloy Degen <degeneloy@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15 11:18:31 +00:00
Subrata Banik 4703edc943 {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.

This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:18:28 +00:00
Subrata Banik 47b836af96 soc/intel/common: Pass `FSPM_UPD *` argument for spd functions
This patch adds `FSPM_UPD *` as argument for
mem_populate_channel_data() and read_spd_dimm().

This change will help to update the architectural FSP-M UPDs in
read_spd_dimm().

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:17:38 +00:00
Subrata Banik 2eb51aace5 {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.

This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:17:25 +00:00
Shelley Chen 5730d018d1 mb/google/herobrine: consolidate hoglin/herobrine QUP inits
Hoglin and Herobrine (proto1) should share majority of GPIOs.
Conslidating the QUP initializations in mainboard.  Also, putting
fingerprint init in a conditional as not all devices will have an FP
sensor.

BUG=b:182963902,b:223826899
BRANCH=None
TEST=booted BIOS on hoglin and check for i2c errors in dmesg

Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14 22:28:56 +00:00
Mars Chen d99e773460 mb/google/trogdor: Add variant Gelarshie
New board introduced to trogdor family.

BUG=b:223101874
BRANCH=none
TEST=make

Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com>
Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14 22:04:26 +00:00
Patrick Georgi 46213f6bbe Documentation: Describe our Coverity Scan integration
Change-Id: I0a2b68a4b4b54c7345280b252d624799316641b1
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-14 19:02:32 +00:00
Felix Singer cf4a3472b9 payloads/seabios: Update stable version to 1.16.0
SeaBIOS 1.16.0 was released on March 2nd. Thus, update the stable
version from 1.14.0 to 1.16.0.

Change-Id: I475a9be47171bfbe3b3c2d4d1d14bb753d8575a8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-03-14 18:18:42 +00:00
Casper Chang f7abb4fccf mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.

BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
     scope enable pin while performing suspend stress and enable pin
     works as expected.
     test suspend stress 1000 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 16:18:52 +00:00