Commit Graph

32 Commits

Author SHA1 Message Date
Kyösti Mälkki 9265f89f4e arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.

Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 12:43:35 +00:00
Elyes HAOUAS a1e22b8192 src: Use 'include <string.h>' when appropriate
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.

Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-20 20:27:51 +00:00
Nico Huber ebd8a4f90c x86/smbios: Untangle system and board tables
We were used to set the same values in the system and board tables.
We'll keep the mainboard values as defaults for the system tables,
so nothing changes unless somebody overrides the system table hooks.

Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-16 16:22:16 +00:00
Elyes HAOUAS 11949990a8 src: Drop unused 'include <arch/ioapic.h>'
Change-Id: I1341f90230f318ac81a4aea24872ff272adad1eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31856
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13 07:29:01 +00:00
Elyes HAOUAS 31f9631548 src: Drop unused 'include <arch/acpigen.h>'
Use <arch/acpi.h> when appropriate.

Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-12 07:27:28 +00:00
Julius Werner cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-08 08:33:24 +00:00
Elyes HAOUAS 0d4de2a477 ACPI: Rename FADT model and set it to zero
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.

So set this value to zero as we are using greater version than ACPI 1.0.

Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01 10:02:29 +00:00
Julien Viard de Galbert cf2b72f951 soc/intel/denverton_ns: Enable ACPI using intelblock
- Port the existing denverton tables to intelblock
- Add C-States table for denverton

Note: Removed code is functionally identical to corresponding
common code.

Tested-on: scaleway/tagada

Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25 11:24:30 +00:00
Elyes HAOUAS 21c8f9cab3 mainboard: Remove useless include <device/pci_ids.h>
Change-Id: I4ee3cc42302c44dc80ae1f285579a4d1775aec16
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-19 05:23:18 +00:00
Arthur Heymans aaced4a932 cpu/intel/common: Use a common acpi/cpu.asl file
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
2018-11-30 22:02:35 +00:00
Elyes HAOUAS 6d19a20f5f mb: Set coreboot as DSDT's manufacturer model ID
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".

Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
2018-11-23 11:00:40 +00:00
Elyes HAOUAS 0cca6e24b7 ACPI: Fix DSDT's revision field
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.

Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 12:12:04 +00:00
Elyes HAOUAS d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h"
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12 09:22:18 +00:00
Elyes HAOUAS 1156b35a23 mainboard: Remove unneeded include <console/console.h>
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29285
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 09:01:13 +00:00
Peter Lemenkov a71b6b3b4c mb/*/*/Makefile.inc: Remove acpi_tables.c from Makefiles
It always included if ACPI is supported since commit 822bc65 with
Change-Id I372dbd03101030c904dab153552a1291f3b63518 ("ACPI: Remove
CONFIG_GENERATE_ACPI_TABLES").

Change-Id: If17a6f43e368ccf850031b349714fa1ec4d02c1d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/28954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-16 17:37:40 +00:00
Elyes HAOUAS e308cc6186 mb: Get rid of unneeded include <cbmem.h>
Change-Id: I80dd65484fd52e9048635091fb20a123e959e999
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27869
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13 15:35:22 +00:00
Julien Viard de Galbert 9d217bf79a mb/scaleway/tagada: Set DIMM slot information from mainboard
This field is not provided by the soc code so add it.

TEST=Check the output of 'dmidecode -t memory'

Change-Id: I6fdf3520da62336a5c654575ed8d1f33eb4f4dc5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-15 11:44:34 +00:00
Julien Viard de Galbert f729cd0b40 mb/scaleway/tagada: Update gpio configuration to use intelblock
Update the gpio configuration structure to the intelblock format.
The resulting configuration is functionally similar (even if some
bits are not identical).

Change-Id: Ide515424c6e1b0cb560b52a7f12909f23fd41e06
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25424
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14 21:03:28 +00:00
Julien Viard de Galbert 7ebb6b0f00 soc/intel/denverton_ns + mb: Rename gpio configuration
In order to use the shared code in intelblock, this patch renames the
denverton specific implementation to not use the same names (for files
and types).

- rename pad_config to remove conflict with soc/.../intelblocks/gpio.h
- rename gpio.c, soc/gpio.h to not conflict with intelblock

Note: There is no functional change in this patch.

Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24926
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14 21:03:04 +00:00
Jonathan Neuschäfer 2f4dde6b9e mb/scaleway/tagada: Document what the selected SMBIOS enclosure type means
This makes the Kconfig file more informative to read.

Change-Id: Icdf4184c8db9cfed4863d9e9f3b714d67f44a4bd
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-13 11:14:11 +00:00
Julien Viard de Galbert 4f226414db mb/scaleway/tagada: populate smbios information
This is done by overriding the weak functions from smbios.c
Some values are hardcoded as they are characteristics of the
Tagada system. Other are retrieved from the BMC through the
bmcinfo interface.

Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23843
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07 21:13:01 +00:00
Julien Viard de Galbert ae6210e500 mb/scaleway/tagada: Override baudrate with bmcInfo
Change-Id: Idd93b64ef91a569127a0713fdb499dff2a1f11db
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07 21:11:59 +00:00
Julien Viard de Galbert fad5c4465f mb/scaleway/tagada: Implement console loglevel override using bmcInfo
Change-Id: I0093cfafe7eaa4a4381e67c9b871fdf28abc470d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07 21:10:50 +00:00
Julien Viard de Galbert 0e755d4f7a mb/scaleway/tagada: Add bmcInfo interface
This interface gives access to configuration information stored in flash
by the Tagada BMC before booting the SoC.

Change-Id: I4351aa11b08bdf65e14706b261c532bbf8837aed
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07 21:10:07 +00:00
Julien Viard de Galbert a8c9efe655 mb/scaleway/tagada: set SMBIOS Enclosure Type in Kconfig
Change-Id: I7acffcf3fc36742c77ce00b253f5b0a68d435798
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24911
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01 13:47:50 +00:00
Julien Viard de Galbert ed089376e3 mb/scaleway/tagada: Remove unused board_id
Change-Id: I6175ce3d3ef739c4f503db826036ffe8feff9ddc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:13:15 +00:00
Julien Viard de Galbert 5a2c7969e9 mb/scaleway/tagada: Update GPIO configuration
Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:12:31 +00:00
Julien Viard de Galbert b424caa25a mb/scaleway/tagada: Remove eMMC configuration
The board does no support eMMC so no need to configure it.

Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:12:21 +00:00
Julien Viard de Galbert d5a1928527 mb/scaleway/tagada: Remove memory down option
The board does not have memory down, only 2 DDR4 Slots.

Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:12:13 +00:00
Julien Viard de Galbert 3c5019dfd9 mb/scaleway/tagada: Update HSIO configuration
Change-Id: I213ea13078fdc28489eb4572a084146df333a31d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:12:03 +00:00
Julien Viard de Galbert bd9ddbcd33 mb/scaleway/tagada: Update device tree
Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:11:55 +00:00
Julien Viard de Galbert 4f13640572 mb/scaleway/tagada: Copy intel/harcuvar and rename
Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:11:42 +00:00