These two da7219_aad properties are optional:
- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
[<2800>, <2900>]
- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
When the Mic Bias Higher Voltage feature is not required, firmware should
just not provide the dlg,micbias-pulse-lvl and dlg,micbias-pulse-time
properties.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:111700809
TEST=On grunt:
No "Invalid micbias pulse level" in dmesg
Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9
Reviewed-on: https://review.coreboot.org/27613
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Akshu Agrawal <akshu.agrawal@amd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Devices using NORTHBRIDGE_INTEL_NEHALEM have an ironlake IGD which does not
support eDP, therefore default to LVDS.
Change-Id: I669c7793a6f78d72899df21b74b9314ef39a29af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27512
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move vboot/tpm specific implementation to vboot.
* Only call functions if CONFIG_FSP2_0_USES_TPM_MRC_HASH is set.
* Preparation for software hash function support, no logic changed.
Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To comply with all relevant bodies throughout the world, SAR settings
take into account the lowest common denominator Tx power settings. This
setup may lead to non-optimal performance when the user location is in a
country that may allow higher power setting. The purpose of Wireless Geo
Delta Settings (WGDS) is to provide offset settings for FCC, Europe,
Japan and Rest of the world. These offsets would be added (by Intel wifi
driver) to the base SAR Tx Power as defined in WRDS and EWRD
BUG=b:65155728
BRANCH=none
TEST=WGDS ACPI table gets created as expected.
Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix a linking problem with VBOOT and USE_OPTION_TABLE enabled.
Make use of cbfs_locate_file_in_region() and always search the
cmos_layout.bin in the 'COREBOOT' region.
With this change applied there's no need to include the vboot_locator
in SMM any more, we can't break NVRAM with different CMOS layouts,
and we keep VBOOT and non VBOOT behaviour the same.
Only include cmos_layout.bin and cmos.default in RO region.
Add notes explaining the decisions.
Tested on Intel Sandybridge, builds and boots with vboot enabled.
Change-Id: I10ae94d7936581bbb5ea49384122062bd4934ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Type of vbt_len should be size_t, change to fix compiler error
Change-Id: I22798fa0edb98fcb9acc1b2dd52f34a61bc511e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.
BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff
With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff
Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.
Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
i2c/alps driver implementation is an exact copy of the i2c/hid driver
with only the addition of ALPS0001_HID. This can be supported by the
i2c/hid driver using the hid field in devicetree which is what glkrvp
mainboard does. So, this change removes the i2c/alps driver which is
anyways unused.
Change-Id: I60761c384f3d800532b2b346272da7be28b77acd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change fixes the issue reported by Coverity CID 1393576 to ensure
that config is checked for NULL before it is actually used.
Change-Id: I5f0cd2bf2437fc640f4cf8d8203a971daf1f8d17
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in
CBFS, but only changed the loader in soc/intel/common, forgetting
the separate one used by FSP 1.1.
As the soc/intel/common loader has now been rolled into the one in
drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one.
Also, remove 2 now-unused header files.
Test: build/boot google/chell, observe display initialized prior
to OS load, no FSP warning in cbmem console due to invalid VBT signature.
Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a new driver for the SX9310 proximity detector device.
The purpose of this is to enable the device's calibration information
to be stored in firmware, and then transferred over to the kernel
via ACPI.
This device has more than 10 individual configuration parameters,
so they would not fit in the generic driver's properties table.
Change-Id: Id8c434eec9fe2da731e142442503a12e88db2236
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27173
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Is unused in the tree.
Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22132
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Shuffle words and drop the _DATA_FILE suffix.
Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This change checks to ensure that config is not NULL before it is
accessed for the first time.
Reported by: Coverity CID #1393312
Change-Id: Ic248c79783da9c2bfdf3b7f737e5963feff7558c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Why would that be a user visible option? Drop the prompt and the
`default n` and select it automatically when needed. I hope I
caught all its users.
TEST=Confirmed that systems with ELOG_GSMI or DEBUG_SMI compile
and link.
Change-Id: I44aeec530cc333f4ed4c8cfe67c7b5c9d8fb0049
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Clean it up and add all flash chip drivers to postcar stage thereby.
There seem to be SPI controllers that don't need the individual
flash chip drivers. For those postcar support was added in b6b1b23
(console/flashconsole: Enable support for postcar). However for
SPI controllers that need the individual drivers (i.e. those with
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y), linking of the postcar
stage was broken.
For all other stages, the set of compilation units stays the same.
Change-Id: Ib8bdb824bfcf2d31ac696e39f797c4355b765756
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26871
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Let the linker take care of it.
Change-Id: I67d2636ceb042f833c1b44888b98135d728940e0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This change adds PCI ID for Intel TP2 Wi-Fi and adds that to
pci_device_ids in Intel wifi driver.
Change-Id: I51abf615fca6001d564e7cd672cc16f3a0fb8dd6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the i210 MACPHY is operated in the SERDES Backplane mode (which
depends on the programmed firmware image), its PCI-ID will be 0x1537.
This does however not change the programming interface for the MAC
address.
Therefore add this new PCI-ID to the driver so that the MAC address can
be programmed in this operation mode as well.
Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/26683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It doesn't make sense to log post codes from a previous (failed) boot
if we are resuming from S3, since the previous boot has to have been
successful in order to enter S3 in the first place.
While we are at it, use a helper function to combine conditionals and
improve readability.
BUG=none
TEST=boot, suspend & resume grunt
Change-Id: I4f3bb8526a0c8c0ea1efd924628b33c147543b88
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26528
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, we were unconditionally adding a TYPE_BOOT message to the ELOG
on every boot (even S3 resume) if CONFIG_ELOG_BOOT_COUNT was disabled.
Now that boot_count_read() returns 0 for the !CONFIG_ELOG_BOOT_COUNT
case, the code becomes a bit simpler.
BUG=b:79865267
TEST=firmware_EventLog
Change-Id: I803fa4c3e03b6cc94751cf0ce34b78021ae2124e
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26527
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a support for generating USB port descriptors for ACPI based
on their definition by the board in devicetree.cb. This will
generate a _UPC and _PLD for each port, using a generic _PLD by
default. The _PLD can also be customized for more accurate
descriptions if necessary.
This sample devictree.cb shows a USB 2.0 type-A port behind a root
hub connected to an xHCI controller:
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB 2.0 Type-A""
register "type" = "UPC_TYPE_A"
device usb 2.0 on end
end
end
end
end
It will generate the following ACPI code in the SSDT:
Scope (\_SB.PCI0.XHCI.RHUB.HS01)
{
Name (_DDN, "USB 2.0 Type-A")
Name (_UPC, Package (0x04)
{
0xFF,
0x00,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "RECTANGLE",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
)
}
Change-Id: I7024390e407fda4b195211bd4755bb5ca53b2b37
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26173
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These methods had unused arguments and could be corrected by
setting the correct number in the method initializer.
Change-Id: I86606cfa1c391e2221cee31994e83667fa9ead61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It is a special case for the Fizz firmware branch, when the device index
is 1, it will check "ethernet_mac" first and then "ethernet_mac0".
For single NIC: config.device_index = "1", maps to "ethernet_mac"
For multiple NICs: config.device_index = "1", maps to "ethernet_mac0"
BUG=b:77836343
BRANCH=Fizz
TEST=Add device index in device tree &&
Program the mac address to VPD in shell
vpd -s ethernet_mac=<mac address> or
vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: I67fd2e999c8f9d8782f294fcafa84b8da970a3a6
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/26051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Had 0x2e hardcoded, which is often the SuperIO chip. Instead,
pull the port from the PNP tree generated from devicetree.cb,
where either 0x4e or 0x2e will be specified.
Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
In 4a3956d7 (drivers/intel/gma, soc/intel/common: improve
cooperation) the vbt_size parameter was not honored leading to
the use of unitialized variables from the caller. Instead, keep
track of if the vbt is already loaded by using the size returned
from the load. If it's non-zero the vbt has been loaded.
BUG=b:79562868
Change-Id: Ia1c47f0d982fae74e0223922f83943c68a846aa9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26236
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
