Add support for the X11SSH-TF which is based on Intel KBL.
Working:
* SeaBIOS payload
* LinuxBoot payload
* IPMI of BMC
* PCIe, SATA, USB and M.2 ports
* RS232 serial
* Native graphics init
Not working:
* TianoCore doesn't work yet as the Aspeed NGI is text mode only.
* Intel SGX, due to random crashes in soc/intel/common
For more details have a look at the documentation.
Please apply those patches as well for good user experience:
Ica0c20255f661dd61edc3a7d15646b7447c4658e
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Adjust CID to allow for Windows driver to attach without breaking
functionality under Linux. Same change made as to google/cyan
(which uses same Realtek RT5650 codec) in commit 607d72b.
Test: build/boot Windowns 10 on google/buddy, observe audio
drivers correctly attached to codec and Intel SST devices.
Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drallion will change debug port UART from 2 to 0. Followed HW
schematic to modify it.
BUG=b:139095062
BRANCH=N/A
TEST=Build without error
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Enable acoustic noise mitgation for hatch platform, the slow slew rates
are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA).
BUG=b:131779678
TEST=waveform test and reduce the noise level.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This removes the need to select ARCH_ARM in SOC Kconfig
Also don't define the default as this result in spurious lines in the
.config.
Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current HWID for drallion is reported as invalid by chrome, generate
new valid HWID with the following command and taking last 4 digits.
`printf "%d\n" 0x$(crc32 <(echo -n '$1'))`
BUG=b:140013681
Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
During boot sequence sometime touchscreen reset keeps failing. Also, kernel
dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message.
This adds around 4 more seconds to the boot sequence. Setting the appropriate
delay of 120ms between enable and reset for Goodix Touchscreen helps to
synchronize and address this failure. This value is 120 ms as per Goodix Spec.
BUG=b:138413748
BRANCH=None
TEST=Built and tested on Hatch system
Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is LVDS bridge, I assume this was lost while upstreaming
or converting boards to variants.
Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Device is present in devicetree but not included in
the build.
Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
New emmc DLL values for Kindred
BUG=b:136784418
BRANCH=none
TEST=Boot to OS 100 times on Kindred proto 1 board.
Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drallion doesn't have on board LAN, remove GBE bin file config.
BUG=b:139906731
TEST=emerge-drallion coreboot chromeos-bootimage and check
image-drallion.bin not include GBE region
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mathew King <mathewk@chromium.org>
Drallion will use soldered down memory. Add dummy spd file.
BUG=b:139397313
BRANCH=N/A
TEST=Build and check cbfs has the dummy spd.bin
Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The file chip.h has a special purpose for defining the
configuration structure used in static devicetree.
Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This provides stack guards with checking and common
entry into postcar.
Change-Id: If0729721f0165187946107eb98e8bc754f28e517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34973
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are required to cover the absensce of .data and
.bss sections in some programs, most notably ARCH_X86
in execute-in-place with cache-as-ram.
Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Board has CAR_GLOBAL_MIGRATION=n and can use .bss for a
variable that was previously declared with CAR_GLOBAL.
Test for !defined(__PRE_RAM__) can be transformed into
ENV_RAMSTAGE here as the warnings about invalid bmcinfo
structure do not need to be repeated in SMM console, which
is generally disabled anyways due to DEBUG_SMI=n.
Change-Id: I6b63213484107fa0eeb0d952d8766916b44a3c4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Kukui AP doesn't remember if the last AP reset was due to AP watchdog.
We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query
the reset reason from EC.
BUG=b:109900671,b:118654976
BRANCH=none
TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog'
2. wait for watchdog reset
3. check 'mosys eventlog list | grep watchdog'
Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
EFP1 is configured as 'DisplayPort with HDMI/DVI
compatibility'. Using this setting 4K monitor is configured
into lower resolution.
Change EFP1 setting to 'HDMI/DVI'
The next addtional small changes are made in VBT:
UEFI GOP Driver
Child Device 2 = LFP
Child Device 3 = EFP1/LFP
LFP Panel configuration Y-Res of Panel #10 = 1920
BUG=N/A
TEST=LCD and HDMI on Facebook FBG1701
Change-Id: Idc694b15ff94b83291a8c8252e269b7e6d96f87b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35043
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.
Test: boot google/link, observe onboard RAM correctly
detected on both channels
Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M)
that’s possible with QEMU on AArch64 virt because it tries to search
the DRAM_SIZE_MB range to find the true memory size.
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In the next board version, we will use GPP_D9 as enable control for touch
screen.
BUG=b:137133946
TEST=build
Change-Id: I213d0878bfca1ce4059ec0393f59d8e79e1b274c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
sx9310 and FPMCU are not used in Kindred.
BUG=none
TEST=build
Change-Id: Ied09d4bdb899d991131a75d7c848ff8637022f53
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When upstreamed, GPIO and RAM config for clapper variant was taken
from an older branch, leading some boards to fail to boot.
Update based on chromium branch firmware-clapper-5216.199.B,
commit 362d845 [baytrail: implement baytrail technical advisory 556192]
Change-Id: I099ee2cd0833e4b9ab093663c4549c79ec044127
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 38dbd68920.
Reason for revert:
ODM helped to verify w/ BT runtime suspend disabled + revert this change
And issue is gone. so I revert this change
see the test result in
https://partnerissuetracker.corp.google.com/issues/136039607#comment32
Change-Id: I248e9613cc39247a2bb88270c234c7d36d0ff60f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
These variants are to support the sarien and arcada boards
with CML SOC, the drallion variant will be used to support the
upcoming drallion board.
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Declare the following panel for Kodama:
- AUO B101UAN08.3
BUG=b:139699622
TEST=builds Kodama image and working properly
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I3f688ffd0ece6afac08d353ab5a6cf1cf876b32f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35001
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The panel description may be pretty large (for example, 1.3k for BOE
TV101) due to init commands and we should only load the right config
when display is needed.
BUG=None
TEST=make -j; boots and see display on Krane.
Change-Id: I2560a11ecf7badfd0605ab189d57ec9456850f75
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
These platforms use different signature for this function, so
declare them with different name to make room in global namespace.
Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Treeya doesn't support the keyboard backlight.
BUG=b:135551210
BRANCH=grunt
TEST=emerge-grunt coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I02dfc77d3cb7ac00b3f10d577d92775db99c1bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.
Reference to Aleena project.
BUG=b:135551210
BRANCH=grunt
TEST=emerge-grunt coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ie0b719ebce90710bca2109b7ff255e19329f9cac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Enable ACPI TBMC notification on tablet mode change to support
convertible treeya devices.
BUG=b:135551210
BRANCH=grunt
TEST=emerge-grunt coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id0618c8df66267b88008dc5057892de6b530629f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Synaptics touchscreen
BUG=b:139699619
TEST=emerge-grunt coreboot chromeos-bootimage
flash bios image to DUT and make sure the touchpad and
touchscreen can work
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I002badd49e678e1c32c802352923ca51efb45cef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
coreboot would clear CMOS by request via IPMI command, for example
BMC can issue "bios-util server --boot_order enable --clear_CMOS"
to set the request and reboot the system, then coreboot would clear CMOS
on the next boot.
Tested on Mono Lake
Change-Id: I21d44557896680cfac3c3b6d83e07b755b242cad
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34857
Reviewed-by: Johnny Lin
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
