Commit Graph

1555 Commits

Author SHA1 Message Date
David Hendricks ceb82da99f add a return type to test function used by xcompile
This fixes a minor bug that could cause testcc to fail unexpectedly.

Change-Id: Ib75d343104b6937682c05acf5232596aac83f105
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2068
Tested-by: build bot (Jenkins)
2012-12-21 20:18:31 +01:00
Zheng Bao a182cbdd62 cbfstool: Align the column of build hint message.
Change-Id: Ic217450411d7fa4e6c3a053be62d7c948dc7145e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2030
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-14 08:46:26 +01:00
Stefan Reinauer cf5aaaf1d2 cbfstool: Catch failing parse_elf_to_payload()
Otherwise cbfstool will segfault if you try to add an x86
payload to an ARM image.

Change-Id: Ie468005ce9325a4f17c4f206c59f48e39d9338df
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2028
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12 06:05:39 +01:00
Stefan Reinauer 1224626e3b Revert "armv7: use __cpu_to_le32 for endianness of reset vector instruction"
This reverts commit 67ce04ea9a

Change-Id: I2781c9275c03bcabf0211e1b6cd1aa8f13005ae0
Reviewed-on: http://review.coreboot.org/2014
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-09 00:00:30 +01:00
Patrick Georgi 198d23c119 crossgcc: Normalize library directories
Various of the build scripts used upstream can't cope with
multilib library paths (eg. lib64), so move things to a place
where they can find them, if such paths are used.

Change-Id: I0dd9bba9a9eadd92d8704157e868fb37c715ee91
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2013
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 08:26:06 +01:00
Stefan Reinauer 10099070ca abuild: Select correct cross compiler for ARMV7 architecture
Change-Id: Ia0dce25a4271299757654ba46baafe6a6673c6d2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2000
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2012-12-08 01:22:17 +01:00
Stefan Reinauer 16bd789a73 buildgcc: Clean up PATH handling
This puts our installed binaries first in the search path, which is what we
really want.

... and remove some dead code
Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I91725af6b0fc486bd943d8e25cdce8d3e2503b3c
Reviewed-on: http://review.coreboot.org/1998
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-08 00:45:09 +01:00
Stefan Reinauer a348d901c7 buildgcc: drop hack to build gcc trunk versions
The focus of the script is to create a supported cross toolchain,
and with GOLD and LTO being released features, we don't need this
anymore.

Change-Id: Ieb7752ce6e143d93414aba5887190f853cbd5a4b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1997
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-08 00:45:03 +01:00
Patrick Georgi 969cd931f8 buildgcc: Remove mingw32 hacks
After patching them to be more flexible, an even better approach was found:
With this change libgcc isn't built at all on mingw32 platforms, so the
system headers aren't necessary anymore.

Now x86_64-pc-mingw32 builds, too.

Change-Id: Ic1406588669d87aee1bcf40ff67af77f2a6ac283
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Raymond Danks <ray.danks@se-eng.com>
2012-12-07 23:44:47 +01:00
Stefan Reinauer 17b24d3fef abuild: produce valid junit files
If no valid cross compiler is found, the junit file produced
by abuild is invalid, missing the closing </testcase> tag.
This breaks proper reporting in Jenkins of our ARM board at
this moment.

Change-Id: I94bfc7f334d33ceeb53451a7c5125058c1f33bd4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1992
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2012-12-07 22:33:16 +01:00
David Hendricks 67ce04ea9a armv7: use __cpu_to_le32 for endianness of reset vector instruction
Change-Id: Ic8f35d7172f6afa933c24774177ed65e6dc579a0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1979
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-07 07:48:18 +01:00
Patrick Georgi fecd26f208 crossgcc: Generalize matching for the mingw case
With this change, i686-pc-mingw32 is acceptable, too.

Change-Id: I924f7ece84e77dc751e5e0318bac1ebc72d39d21
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1972
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-06 23:18:55 +01:00
Stefan Reinauer cb0895470e Fix xcompile (again)
After cherry-picking change 1679 it became apparent that there was a small
typo in my last xcompile change. With this patch applied, I can now compile
the first few files in the tree before GCC dies with

In file included from src/arch/armv7/lib/romstage_console.c:23:0:
src/include/uart.h:31:6: error: redundant redeclaration of 'uart_init' [-Werror=redundant-decls]

Now for some fun...

Change-Id: Idbb07f609e4a240238964cc16714639f5ef09914
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1970
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-06 04:48:51 +01:00
Stefan Reinauer e42133f33e Fix xcompile for ARMv7 and our cross toolchain
The naming of architectures is highly inconsistent between
the different components of the toolchain. In binutils, the
file architecture is elf32-littlearch. In GCC it's armv7a-eabi.
This patch adds support for different BFD / GCC names

Change-Id: Ib644f71e8d8b4964adec73eed23921d3838e8aa7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1969
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-06 02:35:07 +01:00
Stefan Reinauer 4266b92db0 crossgcc: Fix buildgcc on Mac OS X
Once again, the compiler we use on Mac OS X had trouble compiling GCC.
Switch to llvm-gcc because that one works with Xcode 4.5.2 and gcc 4.7.2.
Also drop the -W flags not known to Xcode from the iasl Makefile, and
drop the --remove-destination option from the copy, because that does not
exist on Darwin.

Change-Id: I9f978f65b5ae7edee2ecdcab337772e7a692bd9b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1967
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06 02:01:42 +01:00
Stefan Reinauer dab4238d10 crossgcc: Add support for building armv7a toolchain
!#%$@ autotools don't support all the platforms gcc and binutils
support. If you try to update to the latest autoconf, it will complain
that you have to use the older one. If I had a penny for every time
autotools broke portability...

Change-Id: I479b6c5f64f1def8dca889884e6a2b0e2ffc1fb8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1966
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-05 01:54:13 +01:00
Stefan Reinauer 8d7115560d Rename devices -> device
to match src/include/device

Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1960
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30 23:59:58 +01:00
Stefan Reinauer 0a9775941d cbfstool: Clean up messages
The output of cbfstool is a little inconsistent in some places.
This patch fixes it.

Change-Id: Ieb643cb769ebfa2a307bd286ae2c46f75ac5e1c1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1955
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30 21:32:02 +01:00
David Hendricks 90ca3b6bd7 Add multi-architecture support to cbfstool
This is an initial re-factoring of CBFS code to enable multiple
architectures. To achieve a clean solution, an additional field
describing the architecture has to be added to the master header.
Hence we also increase the version number in the master header.

Change-Id: Icda681673221f8c27efbc46f16c2c5682b16a265
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1944
Tested-by: build bot (Jenkins)
2012-11-30 00:42:31 +01:00
Zheng Bao 6d1fcd5e0b crossgcc: Only build iasl in acpica.
Other acpica's modules are not needed.

Change-Id: I16846caa922aded8db7c1d9e64c007fb2772ff98
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2012-11-29 12:10:28 +01:00
Kyösti Mälkki e773c92ef4 Make mainboard_ops and mainboard.c file optional
This provides weak empty declaration for mainboard_ops.
The struct chip_operations is not defined for __PRE_RAM__ so
the declaration is also moved upwards in the output.

Change-Id: I101f0b8b9f0a55fb51a7c6475d53cc588c84026d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1931
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29 10:25:13 +01:00
Patrick Georgi f33e395213 build system: Split linking into multiple steps
After collecting dependencies for ramstage, add an intermediate step
in which object files are linked per directory. The results are then
linked into the final binary.

This reduces the maximum command line length and might also help with
future use of LTO linking.

Also adapt the lint test for build dir handling, since printall
doesn't provide individual object files for ramstage anymore.

Change-Id: Ie40febd8c1eaf4609944eedeab46d870639e53df
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 22:02:02 +01:00
Patrick Georgi b6f765e7c8 Provide weak empty declarations of all chip_ops used on a board
sconfig creates empty defaults for all chip_ops, which can be overridden
by drivers simply by providing a concrete implementation.

Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1567
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 21:48:22 +01:00
Patrick Georgi 1a5301dd33 abuild: only rebuild boards if requested or after a broken build
That used to be the behaviour, and it's quite useful to incrementally
fix bugs across the tree.

Change-Id: I3e30cbdcf01631bc29f892054caa3babb0969beb
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1888
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 10:07:54 +01:00
Zheng Bao 536b53ea6d xcompile: Add missing XGCCPATH
XGCCPATH is missing in new xcompile.

Change-Id: I177f54189be445404a4a61419064d3c414b8a30c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1921
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 09:22:10 +01:00
Ronald G. Minnich e820e5cb3a Make xcompile support multiple architectures
With this change the the xcompile script now creates environment variables
for more than one architecture.

Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Change-Id: I349a1fd1d865ef16979f1dfd6aeca12b1ee2eed6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1915
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-11-27 02:06:07 +01:00
Idwer Vollering 6b11c8be45 crossgcc: update to acpica-20121114
Update acpica to release 20121114 and
update patches/ to build with this version of acpica.
Correct the creation of crossgcc-build.log
Bump CROSSGCC_VERSION.

Change-Id: I269454ebc3c78b5852e4a67e55bb5642edad191d
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1861
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24 08:54:53 +01:00
Patrick Georgi 0a3f2393ae crossgcc: properly test for flex
This is no GNU tool, so testing for "GNU" in the version string
is bound to fail.
We now accept everything that returns success on "flex --version"
and then hope for the best.

I tested both cases

Change-Id: If325f613fde1648847b998b7e8e5782d0f22b484
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1884
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-22 08:08:48 +01:00
Kyösti Mälkki 1a2a6eebc5 Cleanup sconfig
Fix side-effects of name translation, treat original name as const.

Change-Id: Iae26be8cefe7db11eeb8e62fce6f3b8bc9c1f4ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/799
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-17 02:12:32 +01:00
Stefan Reinauer 17b77ab6aa buildgcc: Print error if flex is missing
flex is needed by acpica. This patch makes the build fail early
instead of after gcc has been compiled, if flex is not there.

Change-Id: Idfd71bdf704ab25de655f1a72c266c5220b15048
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1860
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16 18:08:06 +01:00
Zheng Bao f6659cac3b nvramtool: fsync for mingw.
Change-Id: Ifdec69ca46ba8cbd3eb154d8f4af4b3cafa8019d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1805
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-14 09:24:56 +01:00
Stefan Reinauer 632175802e cbfstool: Rework to use getopt style parameters
- Adding more and more optional and non-optional parameters
  bloated cbfstool and made the code hard to read with a lot
  of parsing in the actual cbfs handling functions. This change
  switches over to use getopt style options for everything but
  command and cbfs file name.
- This allows us to simplify the coreboot Makefiles a bit
- Also, add guards to include files
- Fix some 80+ character lines
- Add more detailed error reporting
- Free memory we're allocating

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ia9137942deb8d26bbb30068e6de72466afe9b0a7
Reviewed-on: http://review.coreboot.org/1800
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 18:38:03 +01:00
Stefan Reinauer 2e200cde9a cbfstool: Update LZMA encoder to LZMA SDK 9.12
This removes almost all C++ code (except the wrapper)

Change-Id: I0f84070e3b6dc57c98d49a53150a140479b3221f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1799
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 18:35:52 +01:00
Vadim Bendebury 7c6b6bb593 cbmem compilation needs to use the hardened toolchain
The appropriate compiler (provided by the build system) is used to
ensure proper toolchain options are used.

cbmem.c is being modified to suppress pointer to integer typecast
warnings.

Change-Id: Ibab2faacbd7bdfcf617ce9ea4296ebe7d7b64562
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1791
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 17:12:23 +01:00
Stefan Reinauer 4a17d29fe8 ifdtool: Dump more registers from FD
Only thing not decoded now are the PCH straps

ifdtool -d path/to/image.bin
File path/to/image.bin is 4096 bytes
Found Flash Descriptor signature at 0x00000010
FLMAP0:    0x02040003
  NR:      2
  FRBA:    0x40
  NC:      1
  FCBA:    0x30
FLMAP1:    0x12100206
  ISL:     0x12
  FPSBA:   0x100
  NM:      2
  FMBA:    0x60
FLMAP2:    0x00210120
  PSL:     0x2101
  FMSBA:   0x200
FLUMAP1:   0x000004df
  Intel ME VSCC Table Length (VTL):        4
  Intel ME VSCC Table Base Address (VTBA): 0x000df0

ME VSCC table:
  JID0:  0x001740ef
    SPI Componend Device ID 1:          0x17
    SPI Componend Device ID 0:          0x40
    SPI Componend Vendor ID:            0xef
  VSCC0: 0x20052005
    Lower Erase Opcode:                 0x20
    Lower Write Enable on Write Status: 0x50
    Lower Write Status Required:        No
    Lower Write Granularity:            64 bytes
    Lower Block / Sector Erase Size:    4KB
    Upper Erase Opcode:                 0x20
    Upper Write Enable on Write Status: 0x50
    Upper Write Status Required:        No
    Upper Write Granularity:            64 bytes
    Upper Block / Sector Erase Size:    4KB
  JID1:  0x001720c2
    SPI Componend Device ID 1:          0x17
    SPI Componend Device ID 0:          0x20
    SPI Componend Vendor ID:            0xc2
  VSCC1: 0x20052005
    Lower Erase Opcode:                 0x20
    Lower Write Enable on Write Status: 0x50
    Lower Write Status Required:        No
    Lower Write Granularity:            64 bytes
    Lower Block / Sector Erase Size:    4KB
    Upper Erase Opcode:                 0x20
    Upper Write Enable on Write Status: 0x50
    Upper Write Status Required:        No
    Upper Write Granularity:            64 bytes
    Upper Block / Sector Erase Size:    4KB

OEM Section:
00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

Found Region Section
FLREG0:    0x00000000
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1:    0x07ff0180
  Flash Region 1 (BIOS): 00180000 - 007fffff
FLREG2:    0x017f0001
  Flash Region 2 (Intel ME): 00001000 - 0017ffff
FLREG3:    0x00001fff
  Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
FLREG4:    0x00001fff
  Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)

Found Component Section
FLCOMP     0x64900024
  Dual Output Fast Read Support:       supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz
  Component 2 Density:                 8MB
  Component 1 Density:                 8MB
FLILL      0x000060c7
  Invalid Instruction 3: 0x00
  Invalid Instruction 2: 0x00
  Invalid Instruction 1: 0x60
  Invalid Instruction 0: 0xc7
FLPB       0x00000000
  Flash Partition Boundary Address: 0x000000

Found PCH Strap Section
PCHSTRP0:  0x0820d602
PCHSTRP1:  0x0000010f
PCHSTRP2:  0x00560000
PCHSTRP3:  0x00000000
PCHSTRP4:  0x00c8e000
PCHSTRP5:  0x00000000
PCHSTRP6:  0x00000000
PCHSTRP7:  0xc0001ae0
PCHSTRP8:  0x00000000
PCHSTRP9:  0x30000580
PCHSTRP10: 0x00410044
PCHSTRP11: 0x99000097
PCHSTRP12: 0x00000000
PCHSTRP13: 0x00000000
PCHSTRP14: 0x00000000
PCHSTRP15: 0x0000033e
PCHSTRP16: 0x00000000
PCHSTRP17: 0x00000002

Found Master Section
FLMSTR1:   0x0a0b0000 (Host CPU/BIOS)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: enabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       disabled
  Host CPU/BIOS Region Read Access:  enabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000

FLMSTR2:   0x0c0d0000 (Intel ME)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      enabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       enabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000

FLMSTR3:   0x08080118 (GbE)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       disabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      disabled
  Requester ID:                      0x0118

Found Processor Strap Section
????:      0x00000000
????:      0xffffffff
????:      0xffffffff
????:      0xffffffff

Change-Id: I68a613df2fd80e097cdea46fbad104d7c73ac9ad
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1756
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-12 06:56:03 +01:00
Vadim Bendebury 6d18fd09c3 Utility to dump boot timing table
Coreboot and u-boot create a table of timestamps which allows to see
the boot process performance. The util/cbmem/cbmem.py script allows to
access the table after ChromeOS boots up and display its contents on
the console. The problem is that shipping images do not include Python
interpreter, so there is no way to access the table on a production
machine.

This change introduces a utility which is a Linux app displaying the
timestamp table. Conceivably the output of this utility might be
included in one of the ChromeOS :/system sections, so it was attempted
to write this procedure 'fail safe', namely reporting errors and not
continuing processing if something goes wrong.

Including of coreboot/src .h files will allow to keep the firmware
timestamp implementation and this utility in sync in the future.

Test:
    . build the utility (run 'make' while in chroot in  util/cbmem)
    . copy `cbmem' and 'cbmem.py' to the target
    . run both utilities (limiting cbmem.py output to 25 lines or so)
    . observe that the generated tables are identical (modulo rounding
      up of int division, resulting in 1 ns discrepancies in some
      cases)

      localhost var # ./cbmem
      18 entries total:

         1:62,080
         2:64,569 (2,489)
         3:82,520 (17,951)
         4:82,695 (174)
         8:84,384 (1,688)
         9:131,731 (47,347)
        10:131,821 (89)
        30:131,849 (27)
        40:132,618 (769)
        50:134,594 (1,975)
        60:134,729 (134)
        70:363,440 (228,710)
        75:363,453 (13)
        80:368,165 (4,711)
        90:370,018 (1,852)
        99:488,217 (118,199)
      1000:491,324 (3,107)
      1100:760,475 (269,150)

      localhost var # ./cbmem.py | head -25

      time base 4249800, total entries 18
      1:62,080
      2:64,569  (2,489)
      3:82,520  (17,951)
      4:82,695  (174)
      8:84,384  (1,688)
      9:131,731  (47,347)
      10:131,821  (89)
      30:131,849  (27)
      40:132,618  (769)
      50:134,594  (1,975)
      60:134,729  (134)
      70:363,440  (228,710)
      75:363,453  (13)
      80:368,165  (4,711)
      90:370,018  (1,852)
      99:488,217  (118,199)
      1000:491,324  (3,107)
      1100:760,475  (269,150)

Change-Id: I013e594d4afe323106d88e7938dd40b17760621c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 03:35:20 +01:00
Stefan Reinauer cb6fd30155 cbfstool: Remove unused cmd_t
Change-Id: Ib1c05828258b9dc7107920ae6cb25bc92ffa86d1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1795
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 03:26:08 +01:00
Stefan Reinauer 20848ee288 cbfstool: add add-flat-binary command to add raw executables
Example:
cbfstool image-link.bin add-flat-binary u-boot.bin fallback/payload \
	0x100000 0x100020
will add u-boot.bin as fallback/payload with a load address of 0x100000
and an entry-point of 0x10002.

Change-Id: I6cd04a65eee9f66162f822e168b0e96dbf75a2a7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 03:25:50 +01:00
Stefan Reinauer 3c53d33c78 ifdtool: Add locking/unlocking and dumping of access permissions
ifdtool will now dump access permissions of system comonents to
certain IFD sections:

Found Master Section
FLMSTR1:   0xffff0000 (Host CPU/BIOS)
  Platform Data Region Write Access: enabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      enabled
  Host CPU/BIOS Region Write Access: enabled
  Flash Descriptor Write Access:     enabled
  Platform Data Region Read Access:  enabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       enabled
  Host CPU/BIOS Region Read Access:  enabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000

FLMSTR2:   0x0c0d0000 (Intel ME)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      enabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       enabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000

FLMSTR3:   0x08080118 (GbE)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       disabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      disabled
  Requester ID:                      0x0118

Also, ifdtool -u /path/to/image will unlock the host's
access to the firmware descriptor and ME region.
ifdtool -l /path/to/image will lock down the host's
access to the firmware descriptor and ME region.

Change-Id: I3e081b80a9bcb398772416f143b794bf307b1c36
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1755
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-09 18:59:42 +01:00
Stefan Reinauer 7a12a32670 Fix abuild output in Jenkins
Ignore the harmless broken pipe messages from "yes"

Building amd/pistachio; i386: ok, using i386-elf-gcc
Using payload /srv/jenkins/payloads/seabios/bios.bin.elf
  Creating config file... (blobs, ccache) yes: standard output: Broken pipe
yes: write error
ok;  Compiling image on 4 cpus in parallel .. ok. (took 10s)

Change-Id: Ic53e246aac3ab6d7ea7a006a8dfac1c3f85797bc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1813
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09 07:05:18 +01:00
Stefan Reinauer 5e93b37310 Fix Segmentation Fault in ifdtool
If a section is bigger than the FD file it is injected into, and the FD
lies about the size of the FD file, ifdtool would crash because reading
in the section writes beyound the FD file in memory.

Change-Id: Idcfac2b1e2b5907fad34799e44a8abfd89190fcc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1754
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09 02:07:08 +01:00
Vadim Bendebury d0b860aada Add utility for parsing/modifying DTD array
Detailed timing descriptor (DTD) is an 18 byte array describing video
mode (screen resolution, display properties, etc.) in Intel Option
ROM. Option ROM can support multiple video modes, specific mode is
picked by the BIOS through the appropriate Option ROM callback
function.

The new utility allows to interpret the 18 byte hex DTD dump, and/or
modify certain values, and generate a new DTD.

To parse the DTD contents just pass the 18 bytes to the utility in the
command line. To modify the existing contents and generate a new dump
precede the 18 bytes with '-m' and follow prompts.

Change-Id: Ib00bdaf42c350b98b5a48d08e6bb347b5ec25a8b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08 20:21:19 +01:00
Vadim Bendebury 00ba25decb Get more informative output from cbmem.py
This is a cosmetic change which formats timestamp information
retrieved by cbmem.py.

Instead of printing timestamps in a single line, print them one per
line and add time (in us) elapsed since the previous timestamp.

     time base 4149594, total entries 18
     1:56,928
     2:58,851  (1,923)
     3:175,230  (116,378)
     4:175,340  (109)
     8:177,199  (1,859)
     9:214,368  (37,168)
     10:214,450  (81)
     30:214,462  (11)
     40:215,205  (743)
     50:217,180  (1,974)
     60:217,312  (132)
     70:436,984  (219,671)
     75:436,993  (8)
     80:441,424  (4,431)
     90:442,487  (1,062)
     99:553,777  (111,289)
     1000:556,513  (2,736)
     1100:824,621  (268,107)

Change-Id: I0d25cafe766c10377017697e6b206276e1a92992
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1716
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08 19:39:06 +01:00
Vadim Bendebury f27d36c361 Fix cbmem to work on 64 bit platforms
For some reason which I fail to understand, specifying endiannes using
'@' (which means 'native' and should be the same as '<' on x86
platforms) causes cbmem.py to crash the machine on 64 bit systems.

What happens is that the addresses read from various table headers'
struct representations do not make sense, when bogus address gets
passed to get_phys_mem, the crash happens while that function is
executed.

dlaurie@ found out that replacing "@" with "<" in fact fixes the
issue. After some investigation I am just submitting this fix without
much understanding of the root cause.

Change-Id: Iaba9bc72a3f6b1d0407a5f1e3b459ccf5063969d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1715
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08 19:38:59 +01:00
Stefan Reinauer a90bd527d9 cbfstool: add offset parameter to create command
CBFS allows coreboot rom images that are only partially covered
by the filesystem itself. The intention of this feature was to
allow EC / ME / IMC firmware to be inserted easily at the beginning
of the image. However, this was never implemented in cbfstool.

This patch implements an additional parameter for cbfstool.

If you call cbfstool like this:
cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000
it will now create an 8M image with CBFS covering the last 1M of
that image.

Test:
     cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000
     creates an 8M image that is 7M of 0xff and 1M of CBFS.

Change-Id: I5c016b4bf32433f160b43f4df2dd768276f4c70b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1708
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08 19:38:26 +01:00
Stefan Reinauer 746d174347 cbfstool: respect dependencies when building locally
cbfstool was not looking at any dependencies when building
by running make in util/cbfstool. By fixing this it's not
required to make clean every time you edit a file in there.

Change-Id: I544fd54d4b9dd3b277996c21ade56dc086b84800
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1707
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-07 18:29:18 +01:00
Kyösti Mälkki a93c3fe7f0 Drop redundant CHIP_NAME in mainboard.c
Compose the name from Kconfig strings instead.

As the field is for debug print use only, a minor change in the output
should do no harm. The strings no longer include word "Mainboard".

Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1635
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06 21:59:21 +01:00
Idwer Vollering 336db54a00 crossgcc: build expat and python in silence
Don't let expat and/or python show the compile process on stdout.
Instead direct this output to crossgcc-build.log.

Fix the logfile path for python.

Change-Id: I431dabf6955d7eef3e54c96d0fb11b92d1cee96d
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1667
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02 20:08:01 +01:00
Nico Huber aa5eae629f inteltool: Add output of 64bit registers in PMBASE
Output values of 64bit registers and fix settings for GPE0_EN for
ICH9/10.

Change-Id: I8ca6b32500331707670972b38466345f581844cd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27 02:54:23 +02:00
Idwer Vollering 573d37da02 crossgcc: update to Python 2.7.3
Change-Id: I9db10e8c7dcd693cc4ab935c587da02dd7eb2bc5
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1621
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27 02:32:11 +02:00
Idwer Vollering 296a015b8a crossgcc: update to expat 2.1.0
Change-Id: Id0b736d402b33138e27b18c74e5ed8ffab0bcccb
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/1620
Tested-by: build bot (Jenkins)
2012-10-27 02:31:58 +02:00
Idwer Vollering cd02793dff crossgcc: update mingw w32api's download URL
Correct the download URL of mingw's w32api.

Change-Id: I98fb43c121399c23f6693ade5cd3b42bc9463724
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1619
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-26 13:03:16 +02:00
Zheng Bao 04ceed6a0f buildgcc: redirect error output to /dev/null
Change-Id: I7cd63248eb8abb711cecce41e3f8a282b34aa126
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1548
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-26 12:51:15 +02:00
Idwer Vollering 908b043da0 crossgcc: update to mingwrt 3.20-2
This patch updates crossgcc to download and compile mingwrt 3.20-2

Change-Id: Ic5ed2df4c3643e469a62c51643d3fc756eb3e615
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1617
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-10-26 01:58:52 +02:00
Idwer Vollering 655a65c139 crossgcc: update to binutils 2.23
This patch updates crossgcc to download and compile binutils 2.23

Change-Id: I75a24ce6fb9f6ac7ae53671314c410b9b0d80aa8
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1615
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 09:24:26 +02:00
Idwer Vollering 7962fc7684 crossgcc: update to MPC 1.0.1
This patch updates crossgcc to download and compile MPC 1.0.1

Change-Id: I7a2a21afc8c26e4fb7b6553c7fd98cc054d01570
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1614
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 09:23:21 +02:00
Idwer Vollering 27efb4cd3f crossgcc: update to MPFR 3.1.1
This patch updates crossgcc to download and compile MPFR 3.1.1

Change-Id: I6c479db5d6d632dcc2201c3771b43e2b663877e1
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1613
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 09:21:51 +02:00
Idwer Vollering fedb63a988 crossgcc: update to GDB 7.5
This patch updates crossgcc to download and build GDB 7.5

Change-Id: I38fc3591396f072ead399b22f516ec765480ea40
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1612
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 09:20:04 +02:00
Idwer Vollering 1cfee0bc10 crossgcc: update to gcc 4.7.2
Update crossgcc to use gcc 4.7.2.
This requires a minor change to util/crossgcc/buildgcc as well.

Tested on hardware with asus/p2b and lenovo/x60.

Change-Id: Ia3921844670ca99741e5715def14dd969f305ab7
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1609
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 06:27:39 +02:00
Idwer Vollering cbd631284d crossgcc: fix compilation of acpica
Compilation of acpica-20120420 is broken (and old, but I'll take care
of that in a future patch),
let's fix that ("Building IASL 20120420 ... failed").

Change-Id: If5fd5cd93d748f78b7c059323f9f810666e32cc7
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1607
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 06:27:17 +02:00
Zheng Bao def50b061d kconfig: Some terms or curses libraries treat backspace as 0x08
Change-Id: Ie4e4a2f0d68643a8f46d24ee7bd1b953e9fe14a5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1605
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-23 05:05:53 +02:00
Zheng Bao 545167252d build: build coreboot on mingw.
regex, pdcurses, wsock(for itohl) are seperated libraries. mmap and unmmap are
ported from git.

Issues:
1. The length of command line is limited. That makes the Thather can not be built
  because too many obj.o need to be built.

Change-Id: I1d60ec5c7720c1e712e246c4cd12e4b718fed05f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22 21:49:54 +02:00
Zheng Bao c31cdd8662 cbfstool: Add -mno-ms-bitfields on (mingw)
The default gcc on mingw will process the __attribute__ ((packed)) in
a different way other than non-win system.

Change-Id: Iac9f4476c922472d0b447f1c3ef60e8e13bd902f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1603
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22 21:49:46 +02:00
Stefan Tauner fba86bfaa8 inteltool: improve the libpci test in the Makefile
Use the verbatim variable method to define and export test code and
the actual libpci test from flashrom. This improves readability and
will work with stricter compiler (settings).

Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1575
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-19 19:32:24 +02:00
Stefan Tauner 1a00cf0632 inteltool: add support for 946GZ and 946PL
Change-Id: Ied0ff16c16d8c2f04b55fe6b0a6ee38966d3c424
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1576
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-19 10:27:53 +02:00
Stefan Tauner 04c06005eb inteltool: new definitions and cleanup
- Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
 - Refine some names and macros.
 - Clean up some whitespace errors.

 - Add IDs and names of 5, 6 and 7 Series southbridges and the three
   latest Core CPU families with integrated memory controllers but do
   not implement any pretty printing routines for them yet.

   The first generation Core family is already supported, although it
   was wrongly named after the PCH and used the wrong ID. Also, the BAR
   values have been mangled to 32b instead of 64b. Both errors have been
   fixed and most basic support for the other two generations was added.

Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1574
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-19 09:57:51 +02:00
Stefan Tauner f450b8619e inteltool: remove bashism from Makefile
&> is a bashism to redirect both outward streams (stdout and stderr), but
with other shells this introduces a race condition with the rm command
after it, because the compiler execution is done in the background/
in parallel. Found and tested with dash.

Change-Id: I08516494828c9f7af168f954f2df027372657867
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1573
Tested-by: build bot (Jenkins)
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-14 22:22:59 +02:00
Zheng Bao 36156ffa1e crossgcc: Allow the non-gnu tar and patch work on XxxBSD
For BSD, patch and tar are not default GNU. Add a work around
to let the non-gun patch and tar work.

Change-Id: I0a9d0bb0e535aa5e0dde146db330c3c8d7b4d8cb
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-14 20:15:46 +02:00
Patrick Georgi c31e3ac258 abuild: allow building with no payload
Change-Id: I167f0bb57bb40f0426182c0abe868bdad58eb120
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1563
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-14 20:10:15 +02:00
Kyösti Mälkki aada2e127b Every chip must have chip_operations
Forcing this rule, chip_ops can be added in the static devicetree
regardless of the existence of the chip.h files.

Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1472
Tested-by: build bot (Jenkins)
2012-10-08 13:24:31 +02:00
Zheng Bao 9b757dccdc lint: Get absolute path in compare_output
The classes in $(top)/Makefile uses $(abspath) to get the path.
The $(abspath) can not resolve symlink. If the coreboot is located
in a symlink directory, the run_printall produces the absolute
path while the $PWD just produces the path with symlink. Use
`pwd -P` to get the abs path.

Change-Id: Icf6b364d030c14a9c78991767b17dafc701baf3c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1551
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-05 22:06:04 +02:00
Zheng Bao 684b8ab309 lint: Stop searching when one GNUmake is found
After make 3.81 is copied to /usr/local/bin, the old make 3.80, which
doesn't work for coreboot, will replace $MAKE with gnumake. That is not
we want.

Change-Id: I87fbe95c70228a22f2c233ff071df29639b63726
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1550
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-04 11:02:02 +02:00
Andriy Gapon 89397fc342 superiotool: Fix for FreeBSD
Makefile still used SVNDEF on FreeBSD.

Change-Id: I45c7fbc66c33e82a2146ef7df87b63bc7edea4cd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1554
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-03 09:26:59 +02:00
Zheng Bao b13e94c2c6 nvramtool: uname in NetBSD doesnt take "-o"
see the Netbsd manual:
http://netbsd.gw.com/cgi-bin/man-cgi?uname++NetBSD-current
Error output needs to be redirected.

Change-Id: I1853a0162e14be0ee9d7971466499af6c72b2427
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-28 14:50:02 +02:00
Zheng Bao 82c06bd2d5 nvramtool: Require no hw access for integrated Makefile
The Makefile.inc is integraged into coreboot Makefile. It doesn't
need to access to HW like cmos. It doesn't include cmos-hw-unix.c,
which is only for individual tools running seperatedly.

Change-Id: Ib00b5c3da63acb4120cb23eb7d661c5bc75d7c86
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1544
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-28 14:49:21 +02:00
Zheng Bao 533bca80ed lint: Add template for mktemp to meet BSD requirements
Change-Id: I86cecf6aee1fcb682cb32bd0f03e014fd1afe594
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1549
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-28 14:46:37 +02:00
Patrick Georgi 80d2526c72 abuild: abort if payload.sh failed
With this chance it becomes practical to have payload.sh build/update
the payload, and abort abuild if something bad happened.

Change-Id: Iee25de2e8b62153c477b8e5d32e097b59797523c
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1536
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-09-25 16:08:53 +02:00
Patrick Georgi 5c63761c37 nvramtool: Read/write binary data as binary
Only relevant on windows (and nvramtool currently fails there), but
it doesn't hurt.

Change-Id: I5d6420c1f9dc49cf3af31e75088e51a90f729e01
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1535
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-09-25 16:08:23 +02:00
Zheng Bao 5b209c0718 crossgcc: Change the term color back (trivial)
Change-Id: I6a7852eef32a3440c9d29e45420cb21d2db8c404
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-20 09:25:46 +02:00
Zheng Bao 615304c667 lint: Dont highlight the matching text in grep
Sometimes we like to make grep auto-highlight the match text by
setting the GREP_OPTIONS. This will make the compare_output
in lint-002 catch the difference between 2 strings which text are
same but color are different. Override the GREP_OPTIONS.

Change-Id: Ia257214fe5149e084e8eac3fb551a494eaa46ae6
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1526
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-17 10:37:21 +02:00
Patrick Georgi b3a18acb56 Isolate Kconfig host compiler options
This reverts commit 645f2dd5d9.

Instead of adding a special case to nvramtool to avoid it
picking up Kconfig's regex.h, have the host compiler only
consider util/kconfig for includes (ie. -Iutil/kconfig)
for kconfig related object files.

Change-Id: Ie4f97ce38cb3e911f6e6c1e5b6f86f6998d93f69
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1509
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-09-14 07:33:07 +02:00
Rudolf Marek 73ab60a9d4 Fix ramstage location in trace scripts
The ramstage location has been changed. Reflect this in the script.

Change-Id: I76c9b38a8ffe2188e94146e845d23536625c0979
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/1504
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-13 10:11:53 +02:00
Zheng Bao 645f2dd5d9 nvramtool: Set build flags for FreeBSD
Set HOSTCFLAGS as nil to make the nvramtool include the regex.h
in system. Otherwise it will include the regex.h in kconfig, which
will cause building error in FreeBSD.

Change-Id: I95292e23e1716da1260842be9597119a4e26c8ed
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1500
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
2012-09-11 10:29:19 +02:00
Zheng Bao 534e61c4e6 nvramtool: Remove the building warning on older gcc
Some older gcc requires the default entry in switch, otherwise
build warning "enumeration value not handled in switch" will come
up.

Change-Id: Ic8ea9960e4aca599e0ea62ec345122c9df57e766
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1501
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-11 08:32:30 +02:00
Stefan Tauner e54995a116 superiotool: Add support for Fintek F81865F/F-I register dump.
Datasheet: http://www.fintek.com.tw/files/productfiles/F81865_V028P.pdf

The code was done by Juha Tuomala <Juha.Tuomala@iki.fi> but he refused
to sign it off, or commit it for review. I'll commit it anyway with my sign-off
because it does not exceed threshold of originality for any copyright.

Change-Id: Id86267f5add539b99229f20bbe339bfb5eb20f8b
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1496
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-06 19:51:05 +02:00
Zheng Bao a5de94128b gitconfig: Match the Change-Id line more exactly
Change-Id: I5ac267770bc5b43dd1435e75ab0fcbde0d88b664
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1487
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
2012-08-27 15:41:33 +02:00
zbao 79b0574698 crossgcc: Update GDB patch version to 7.4.1
libgen.h dont have to be included.

Change-Id: I46a6a23a310b20784de956a577f1ab3c7931e34d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1470
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-23 07:02:55 +02:00
Kyösti Mälkki fee73df07a Auto-declare chip_operations
The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-22 05:06:41 +02:00
zbao 2efabba468 buildgcc: Remove the warning options unsupported by cygwin
My cygwin hostcc doesn't support
-Wempty-body -Waddress -Wmissing-field-initializers

Change-Id: I879e05f3bd396b36b327f204252e820552b6e12e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1426
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-15 08:09:58 +02:00
zbao 844e01357b buildgcc: Update the toolchain patches version
acpica 20120420, acpica-unix-20110922_no_unused_variables.patch is not
used anymore.
binutils 2.22.

Change-Id: I58459bd2eba2ad752fc033e51ee0892e2e069a02
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1424
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-14 15:44:20 +02:00
Stefan Reinauer a675d49408 Fix SMBIOS generation
Dropping mainboard's chip.h broke execution of the mainboard's enable
function and the addition of mainboard specific smbios tables.

The former was fixed by Kyosti in http://review.coreboot.org/1374
This patch fixes the breakage in static.c and also backs out a small
portion of Kyosti's patch (because it's not needed anymore)

Change-Id: I6fdea9cbb8c6041663bd36f68f1cae4b435c1f9b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1421
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-08 11:34:57 +02:00
Stefan Reinauer 57879c9bd1 Make the device tree available in the rom stage
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
   compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
   the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
   romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage

We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.

So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
 #ifndef __PRE_RAM__
        .ops = 0,
 #endif
        .bus = &_dev7_links[0],
        .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
        .enabled = 0,
        .on_mainboard = 1,
        .subsystem_vendor = 0x1ae0,
        .subsystem_device = 0xc000,
        .link_list = NULL,
        .sibling = &_dev22,
 #ifndef __PRE_RAM__
        .chip_ops = &southbridge_intel_bd82x6x_ops,
 #endif
        .chip_info = &southbridge_intel_bd82x6x_info_10,
        .next=&_dev22
};

Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-04 18:05:39 +02:00
Stefan Reinauer 188e3c2ff0 Drop mainboard chip.h
mainboard_config never worked right, at least not since we've had sconfig.
Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that
tried to use it anyways.

Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1359
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26 22:57:35 +02:00
Stefan Reinauer a9f670a760 ifdtool: Use perror for file write errors
The "Error while writing." error messages did not output a new line
which made the output look weird. With this patch, it should look like
this:

$ ifdtool -x 3rdparty/mainboard/google/parrot/descriptor.bin
File 3rdparty/mainboard/google/parrot/descriptor.bin is 4096 bytes
Found Flash Descriptor signature at 0x00000010
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
Flash Region 1 (BIOS): 00200000 - 007fffff
Error while writing: Bad address
Flash Region 2 (Intel ME): 00001000 - 001fffff
Error while writing: Bad address
Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)

Change-Id: I784ff72d0673f167dbf0bd10921406abd685ce72
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1299
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-07-24 10:13:33 +02:00
Anton Kochkov 59b36f1026 msrtool: Factor out cpuid() from target probe functions into main()
Almost all probe functions called cpuid(). Those calls are replaced
by a single cpuid() call in main() and a new parameter to the target
probe functions with the cpuid() result.

The vendor_t and struct cpuid_t definitions are moved closer to the
top of msrtool.h and the vendor_t enum is reformatted to simplify
addition of further values.

Change-Id: Icd615636207499cfa46b8b99bf819ef8ca2d97c0
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/1259
Tested-by: build bot (Jenkins)
2012-07-21 17:35:46 +02:00
Anton Kochkov c7fc4422a0 inteltool: Add support for H65 Express chipset
Added few MCH and DMI registers for H65E.
Description of them can be found at
"2nd Generation Intel Core Processors
Family datasheet"

Change-Id: If4fee35bb5a09b04ea0684be9cbd3c1e9084b934
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1258
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-21 16:06:41 +02:00
Patrick Georgi 116327ee06 sconfig: typo fix
eliminate printf format warning.

Change-Id: I51f75a259d28c5de788f57c3d720b76ca638e330
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1248
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-20 13:11:46 +02:00
Mathias Krause 41c229c029 cbfstool: signed vs. unsigned fixes
Use the right data types to fix compiler warnings.

Change-Id: Id23739421ba9e4a35599355fac9a17300ae4bda9
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1236
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:35 +02:00
Mathias Krause 5c581c4d6c cbfstool: provide a prototype for remove_file_from_cbfs
To complement commit e1bb49e (Add a "remove" command to cbfstool) and
fix a compiler warning provide a prototype for remove_file_from_cbfs.

Change-Id: Ied8eac956de5fed3f9d82ce1e911ee1fec52db15
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1235
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:27 +02:00
Mathias Krause d2567c8d92 cbfstool: make endian detection code more robust
Accessing the memory of a char array through a uint32_t pointer breaks
strict-aliasing rules as it dereferences memory with lower alignment
requirements than the type of the pointer requires. It's no problem on
x86 as the architecture is able to handle unaligned memory access but
other architectures are not.

Fix this by doing the test the other way around -- accessing the first
byte of a uint32_t variable though a uint8_t pointer.

Change-Id: Id340b406597014232741c98a4fd0b7c159f164c2
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1234
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:15 +02:00