Commit Graph

44511 Commits

Author SHA1 Message Date
Felix Held 5911096e06 cpu/x86/mp_init: use cb_err as start_aps return type
Using cb_err as return type clarifies the meaning of the different
return values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icb96f28b4d59b3d00638a43c927df80f5d1643f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58455
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20 17:28:52 +00:00
Felix Held b5376ff972 cpu/x86/mp_init: add final new line to debug messages
Since during AP startup it's not guaranteed that no AP console output
will be printed between consecutive printk calls in send_sipi_to_aps,
add a new line character to all printks to make sure to have the outputs
from the APs on separate lines. For consistency also add a final new
line character to the printk call in start_aps.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3983b8a0e6b272ba5fb2a90a108d17a0c480c8b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58454
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20 17:28:33 +00:00
Felix Held b04e2bae77 cpu/x86/mp_init: factor out send_sipi_to_aps function
Apart from the SIPI number in the debug message the two instances of the
SIPI sending code in start_aps are identical, so factor it out into a
new send_sipi_to_aps function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a921b81fce77fbf58c7ae3b50efd8c3e6e5aef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58453
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20 17:28:18 +00:00
Felix Held edc5af552a cpu/x86/mp_init: use types.h include
Using types.h as include instead of stddef.h and stdint.h will also
provide commonlib/bsd/cb_err.h which will be used in follow-up patches.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I08a68dc827d60c6c9a27b3ec8b74b9c8a2c96d12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58452
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20 17:28:09 +00:00
Raul E Rangel 41ba01bb95 util/cbfstool/rmodule: Omit undefined extern symbols from reloc table
When using `DECLARE_OPTIONAL_REGION`, it is assumed that
REGION_SIZE(name) == 0 if the region was not defined in the memlayout.
When using non-rmodule stages (i.e., bootblock, romstage, etc), this
assumption holds true, but breaks down in rmodule (i.e., ramstage)
stages.

The rmodule tool is not currently omitting undefined externals from the
relocation table. e.g.,

    extern u8 _##name##_size[];

This means that when the rmodule loader runs, it will rewrite the symbol
from 0 (which is the default the linker assumed) to 0 + offset. This is
wrong since the symbol doesn't actually exist. Instead we need to omit
the relocation so it continues to keep the default value of 0.

BUG=b:179699789
TEST=Print out REGION_SIZE(cbfs_cache) in ramstage and verify it is set
to 0.
I also see the following printed by the rmodtool now:

DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone_size
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone
DEBUG: Omitting relocation for absolute symbol: _stack_size
DEBUG: Omitting relocation for absolute symbol: _program_size
DEBUG: Omitting relocation for absolute symbol: _cbmem_init_hooks_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache
DEBUG: Omitting relocation for undefined extern: _cbfs_cache
DEBUG: Omitting relocation for undefined extern: _cbfs_cache_size

As you can see the _watchdog_tombstone will also be fixed by this CL.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib57e263fa9014da4f6854637000c1c8ad8eb351a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20 15:56:28 +00:00
Raul E Rangel 3f41d3269e lib/cbfs: Call rdev_unmap on hash mismatch
We don't want to leak any mappings.

BUG=b:179699789
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibcd28ce12cbd5e221e8f4fa910fd8472bedb802f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20 15:55:21 +00:00
Michael Niewöhner 4396358fd3 kconfig_lint: use just one variable for keeping track of choices
Instead of using two variables, one for the boolean value and one for
the path, use just one with the path. Since an empty string evalutes to
false, this simplification does not change behaviour.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2f1171789af6815094446f107f3c634332a3427e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20 15:52:16 +00:00
Michael Niewöhner 70fb5cb514 kconfig_lint: put $inside_choice together right in the first place
Instead of substituting the delimiter later, put $inside_choice together
right in the first place.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia713510a683101c48c86a1c3722ebb1607a29288
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20 15:51:36 +00:00
Raul E Rangel a76e647094 soc/amd/common/block/cpu: Remove magic number in memlayout
The SPI DMA controller can only perform transactions on a cache line
boundary. This change removes the magic number and uses the #define to
make it clear.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20 15:49:23 +00:00
Bora Guvendik fbf874fb38 soc/intel/alderlake: Fix wrong FIVR configs assignment
For PchFivrExtVnnRailSxEnabledStates, vnn_enable_bitmap config is used
by mistake, instead of the expected vnn_sx_enable_bitmap

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Idf100be3ac4d6d97335c627e790c1870558d1210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20 15:48:38 +00:00
Bernardo Perez Priego 24e3d67004 mb/intel/adlrvp_m: Enable touchpad
These changes include ELAN touchpad to ACPI tables and configure GPIO's.

BUG=None
Test=Boot board, touchpad should be functional

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-20 15:48:22 +00:00
Bernardo Perez Priego 0a1602217f mb/intel/adlrvp: Remove EC region
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ic76c29069beb510dd7620f340e0aab212668c3f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-20 15:48:09 +00:00
Kangheui Won 26bb4aa1ad psp_verstage: remove psp_ef_table struct
psp_efs.h now has embedded_firmware struct which is copied from
amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to
remove duplicates.

TEST=boot on zork and guybrush

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-20 15:47:29 +00:00
Wisley Chen aaa3b57a44 mb/google/brya/anahera: Add two thermal sensor setting
Anahera has 4 thermal sensors, so add the missing sensors settings.

BUG=b:203187535
TEST=build and verified by thermal team.

Change-Id: I0e5c0d9c09c88cc95fdfd77b96800a0f4929d7d2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20 15:47:00 +00:00
Wisley Chen a714848140 mb/google/brya/anahera: Update HID to MX98360A
Because of a change in the chromium OS kernel machine driver for
the MAX98357A, a _HID that matches MAX98360A has to be used.
(https://chromium-
review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268/)


BUG=b:200778066
TEST=FW_NAME=anahera emerge-brya coreboot

Change-Id: Ic68373920d9135e614ff792149079de451ec6e60
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20 15:46:46 +00:00
Kevin Chang e3bb49e905 mb/google/taeko: enable DPTF functionality for taeko
Enable DPTF functionality for taeko

BRANCH=None
BUG=b:203035930
TEST=Built and tested on taeko board

Change-Id: Ic9f3cbf5cd52ebc48b274b43fcdb57a51dcf94ec
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-10-20 15:46:33 +00:00
Wisley Chen dd275f7a6c mb/google/brya/var/anahera: change from CLKREQ#2 to CLKREQ#6 for eMMC
Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6

BUG=b:197850509
TEST=build and boot into eMMC

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20 15:46:03 +00:00
Seunghwan Kim cb58810426 mb/google/dedede/var/bugzzy: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL

BUG=None
TEST=emerge-dedede coreboot

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20 15:45:07 +00:00
Seunghwan Kim aa02363e68 mb/google/dedede/var/sasuke: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL

BUG=None
TEST=emerge-dedede coreboot

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I91183f33b92569dd49967ef866d58043d79c287b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20 15:44:56 +00:00
Michael Niewöhner bc5f51fa56 soc/intel/{skl,apl}: don't run or even include SGX code if disabled
Do not run or include any code in case the user did not explicitly
enable SGX through `SOC_INTEL_COMMON_BLOCK_SGX_ENABLE`.

Also move the ifdef inside the ASL file.

Change-Id: Iec4d3d3eb2811ec14d29aff9601ba325724bc28c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-10-20 15:42:51 +00:00
Joey Peng e874375394 mb/google/brya/var/taeko: Add fw_config probe for ALC5682-VS
ALC5682-VD/ALC5682-VS load different kernel driver by different _HID.
Update the _HID depending on the AUDIO field of fw_config.Define fw
config bit 5-7 in coreboot for codec.

BUG=b:202913837
TEST=FW_NAME=taeko emerge-brya coreboot

Change-Id: I635b173e0fe4c46d28f2c29fecee1998b29499b1
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20 14:26:50 +00:00
Felix Singer a61e781e4b mb/intel/jasperlake_rvp: Rework Kconfig
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_JASPERLAKE_RVP_COMMON`, which is used as base for each
variant.

Also, move selects from Kconfig.name to Kconfig that the configuration
is at one place and not distributed over two files.

Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.

Change-Id: Ic7552195ed5a3ae6ab8e456d7d38d5539a052009
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-20 09:55:21 +00:00
Patrick Georgi d23981998c soc/intel/skl: Constify `soc_get_cstate_map()`
This is a follow-up to commit e9f10ff38b which changed the base
signature and all other occurrences.

To make gcc11 happy (which is pickier about these things), let skylake
follow.

Change-Id: I42a629d865baa53640213a03e54e85623a386e35
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58458
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-19 20:47:46 +00:00
Felix Singer e07f9ccc11 mb/intel/kblrvp: Rework Kconfig
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_KBLRVP_COMMON`, which is used as base for each
variant.

Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.

Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-19 18:55:12 +00:00
Felix Singer e4047354ec mb/intel/coffeelake_rvp: Rework Kconfig
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each
variant.

Also, move selects from Kconfig.name to Kconfig so that the
configuration is at one place and not distributed over two files.

Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.

Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
2021-10-19 18:55:00 +00:00
David Wu 2d2cc0dcb9 mb/google/brya/var/kano: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.

BUG=b:192137970
TEST=FW_NAME=kano emerge-brya coreboot and boot to OS.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I20bf5ca66c6d05229c6d72058c5a73f38a58be3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:48:19 +00:00
Furquan Shaikh d0975ff5d5 soc/intel/common/block/cse: Use newly added `create-cse-region`
This change uses the newly added `create-cse-region` command for
cse_serger tool instead of performing `dd` operations for each
partition.

BUG=b:189177580

Change-Id: Ia915e3ac423f9461876e9ae186fb8ddce55f3194
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:32:30 +00:00
Furquan Shaikh bf848ad4b2 util/cse_serger: Add command `create-cse-region`
This change adds a new command `create-cse-region` to cse_serger tool
which takes as inputs offset:size and file for different CSE
partitions and generates the entire CSE region image.

BUG=b:189177186

Change-Id: Ib087f5516e5beb6390831ef4e34b0b067d3fbc8b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:32:24 +00:00
Furquan Shaikh 8b4ca15d7e util/cse_serger: Replace cse_layout_regions with array of regions
This change replaces `struct cse_layout_regions` with an array of
`struct region` and introduces enums for DP and BP[1-4]. This makes it
easier to loop over the different regions in following changes.

BUG=b:189177186

Change-Id: If3cced4506d26dc534047cb9c385aaa9418d8522
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:10:12 +00:00
Furquan Shaikh 5d8f4badda mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B
CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region
in case of firmware update. Ensure that the size of the regions match
so that we do not have situations where ME_RW_A/B firmware grows
bigger than what CSE_RW can hold.

BUG=b:189177538

Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:10:02 +00:00
Furquan Shaikh 3f0d64329c soc/intel/common/cse: Support RW update when stitching CSE binary
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config.

BUG=b:189177580

Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:09:49 +00:00
Furquan Shaikh 0a0182e13d mb/google/brya: Add sub-regions to SI_ME in chromeos.fmd
This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.

BUG=b:189177538

Change-Id: I4da677da2e24b0398d04786e71490611db635ead
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:09:41 +00:00
Furquan Shaikh f888c682f8 soc/intel/alderlake: Enable support for CSE stitching
This change enables support for stitching of BP1 and BP2 partitions
for CSE. This currently mimics what Intel FIT tool does w.r.t. adding
different components to the different partitions.

BP1:
* Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP.
* Decomposed components from CSE FPT file: RBEP, MFTP.
* Input components: PMCP, IOMP, NPHY, TBTP, PCHC.

BP2:
* Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP.
* Decomposed components from CSE FPT file: RBEP, FTPR, NFTP.
* Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP.

BUG=b:189177580,b:189177538

Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:09:26 +00:00
Furquan Shaikh 6ef863c5c4 soc/intel/common/cse: Add support for stitching CSE components
This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout

In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout  : CSE_LAYOUT
4. Data    : CSE_DATA

Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.

Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.

These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.

BUG=b:189177580

Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:09:08 +00:00
Furquan Shaikh 3959aa6351 southbridge/intel/common: Add an option to allow stitching of CSE binary
In the following changes, CSE binary for some platforms will be
stitched at build time instead of adding a pre-built binary. This
change adds a new Kconfig `STITCH_ME_BIN` which allows mainboard to
select if it wants to stitch CSE binary instead of adding a pre-built
one. In this case, ME_BIN_PATH is not visible to user and instead
mainboard and/or SoC code is expected to provide the recipe for
stitching the CSE image.

BUG=b:189177580

Change-Id: I78ab377e110610f9ef4d86a2b6eeb4113897df85
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:58 +00:00
Furquan Shaikh 555f040772 util/cse*: Add cse_helpers.{c,h}
This change moves `read_member` and `write_member` helper functions
out of cse_fpt.c and cse_serger.c into cse_helpers.c to avoid
duplication.

BUG=b:189177186,b:189167923

Change-Id: I7b646b29c9058d892bb0fc9824ef1b4340d2510c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:45 +00:00
Furquan Shaikh d7fb6a90e1 util/cse_serger: Add a new tool for stitching CSE components
This change adds a new tool `cse_serger` which can be used to print,
dump and stitch together different components for the CSE region.

BUG=b:189177186

Change-Id: I90dd809b47fd16afdc80e66431312721082496aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:24 +00:00
Furquan Shaikh 796aeeba96 util/cse_fpt: Add a new tool for managing Intel CSE FPT binaries
This change adds a new tool `cse_fpt` which can be used to print and
dump CSE partitions in Flash Partition Table (FPT) format.

BUG=b:189167923

Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:03 +00:00
Angel Pons afd268a0cb cpu/intel/speedstep: Constify `get_cst_entries()`
Make the `get_cst_entries()` function provide a read-only pointer. Also,
constify the actual data where applicable.

Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19 15:00:01 +00:00
Angel Pons e9f10ff38b soc/intel: Constify `soc_get_cstate_map()`
Return a read-only pointer from the `soc_get_cstate_map()` function.
Also, constify the actual data where applicable.

Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19 14:57:59 +00:00
Angel Pons d2794cea12 acpi/acpigen: Constify CST functions' pointers
The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry`
functions don't modify the provided C-state information. So, make the
pointer parameters read-only to enforce this. Also constify arguments
where possible.

Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-19 14:57:39 +00:00
Angel Pons 14643b33b0 soc/intel/*/acpi.c: Don't copy structs with `memcpy()`
A regular assignment works just as well and also allows type-checking.

Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19 14:57:17 +00:00
Tim Wawrzynczak 3b9be63bd3 arch/x86: Increase MAX_SMBIOS_SIZE
With the recent addition of SMBIOS table 20, the cbmem area on
google/brya0 overflows and

ERROR: Increase SMBIOS size
SMBIOS tables: 2128 bytes.

is seen in the logs.

Therefore, double the size of the SMBIOS area from 2 KiB to 4 KiB to
accomodate more tables as needed. This happens during ramstage so 2k
is not a big deal at this point.

Change-Id: I43aa6a88d176e783cc9a4441b35b8d608c4101cd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-19 14:40:09 +00:00
Felix Held 3c1c90bf61 soc/amd/common/block/include/psp_efs: don't typedef struct
Don't use a typedef for the embedded_firmware struct so that it's
clearer that this is a struct.

TEST=Timeless build for google/guybrush results in identical binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97a02c350af57c8f58014aaf7dda8b4796905ff3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19 12:35:17 +00:00
Felix Held ad68b07d45 util/amdfwtool: rename PSP related embedded_firmware struct elements
The element at offset 0x14 in the embedded_firmware struct is the
pointer to the combo PSP directory header, so rename it from comboable
to combo_psp_directory to clarify that this is not a flag, but a pointer
to a data structure. Also rename psp_entry to psp_directory since it
points to the PSP directory table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19 12:35:08 +00:00
Felix Held 35360a9e66 soc/amd/common/block/include/psp_efs: rename embedded_firmware elements
The element at offset 0x14 in the embedded_firmware struct is the
pointer to the combo PSP directory header, so rename it from comboable
to combo_psp_directory to clarify that this is not a flag, but a pointer
to a data structure. Also rename psp_entry to psp_directory since it
points to the PSP directory table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia70e97f10f4fa0ac63cc65a33ecdc956538482b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19 12:34:58 +00:00
Kenneth Chan 768cb760e1 mb/google/guybrush/dewatt: update DRAM table
Samsung LPDDR4X 4266 2G K4U6E3S4AB-MGCL
Hynix  LPDDR4X 4266 2G H54G46CYRBX267
Micron LPDDR4X 4266 2G MT53E512M32D1NP-046 WT:B
Micron LPDDR4X 4266 4G MT53E1G32D2NP-046 WT:B

BUG=b:203014978
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I31ec5b84b5ad2e8d0aedf41ceb56f9e5f7fa538a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58313
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-19 12:30:46 +00:00
Furquan Shaikh 2bfef8d856 cbfstool: Add helper function `buffer_from_file_aligned_size`
This change adds a helper function `buffer_from_file_aligned_size`
that loads a file into memory buffer by creating a memory buffer of
size rounded up to the provided `size_granularity` parameter.

BUG=b:189177186,b:189167923

Change-Id: Iad3430d476abcdad850505ac50e36cd5d5deecb4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-18 21:15:41 +00:00
Nico Huber 967730f565 kconfig_lint: Drop overly restrictive rule about choice configs
This rule was creating trouble:
* A symbol may only be declared inside or outside a choice.

The linter treats every occurence of a `config` entry as a symbol
declaration, even when it's just setting a default or adding selects.
This is not easy to fix as the symbol objects are not created first
and then added to the $symbols array when we know what kind of decla-
ration we have, but are created incrementally inside this global
list.

Change-Id: I48a17f6403470251be6b6d44bb82a8bdcbefe9f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56410
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18 19:33:57 +00:00
Ravi Kumar Bokka dcb26139ca sc7280: Add GSI FW download support
Add GSI Firmware download support for QUP wrappers.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I68c106c942acadc752351f03843d93612cf9c19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-18 18:28:53 +00:00