Commit Graph

47527 Commits

Author SHA1 Message Date
Arthur Heymans 95af254e11 cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub
The sinkhole exploit exists in placing the lapic base such that it
messes with GDT. This can be mitigated by checking the lapic MSR
against the current program counter.

Change-Id: I49927c4f4218552b732bac8aae551d845ad7f079
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 14:12:27 +00:00
Frans Hendriks 8304ca4cb6 src/mb/facebook/fbg1701: Remove IGNORE_IASL_MISSING_DEPENDENCY
CB:63242 solves the missing dependency on _PRS.

The config IGNORE_IASL_MISSING_DEPENDENCY can be removed.

BUG=N/A
TEST=Boot facebook FBG1701

Change-Id: I014a9078cb12908c515a978e4111ff9facc9e443
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 14:09:54 +00:00
Frans Hendriks a03498f302 src/mb/facebook/fbg1701/acpi/superio.asl: Remove _PRS
IASL report warning since _SRS is required.

Fixed configuration is always enabled.
_CRS is sufficient, remove _PRS

BUG=N/A
TEST=Boot facebook FBG1701

Change-Id: Ib9e004e192bc7f9680c3728ce7c60d56f1a13945
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 14:09:44 +00:00
Lean Sheng Tan d8bfe12257 mb/prodrive/atlas: Configure eSPI IO decode ranges for EC
This implementation adds eSPI IO decode range for EC.
1. 0x800-0x8FF / 0x200-020F: EC host command range.
2. 0x900-0x9ff: EC memory map range.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I787561287025e33a8622eb9b3565fa14d0416c46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 14:01:05 +00:00
Lean Sheng Tan ed74918f4e mb/prodrive/atlas: Disable ASPM for i225 port
I225 doesn’t support ASPM, so disable it at the root port.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I61fe3760c1cde60795c9b52c703e521ba4df504a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 14:00:32 +00:00
Elyes Haouas 84ef4fb15b util/lint/checkpatch.pl: Update to v5.18-2 lines related to "codespell"
Change-Id: I55cc4255ea88723c813a04d87e4c028c64f92dbd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-04-11 13:59:59 +00:00
Sean Rhodes f2d162efca payloads/tianocore: Don't declare tools directory twice
EDK_TOOLS_PATH is set on lines 85 and 137. Remove the instance
on 85. edk2 still builds correctly.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0c837f14693941afec194b140c93d786ea784e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 13:59:29 +00:00
Lean Sheng Tan faf66f2483 mb/prodrive/atlas: Update GPIOs
Update Atlas GPIOs for GPD11 & E7.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I92a0d0797206cdba96d7c6efe264b0356b5157ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 13:59:04 +00:00
Lean Sheng Tan 044883615d mb/prodrive/atlas: Update correct SPD address
Update the SPD address as Atlas is using DIMM 0 & 1 in memory
controller 1 channel 1.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Icefcd23b57a7f97e1ee25fed20b35d0e2cb51145
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 13:58:26 +00:00
Arthur Heymans ff69b6f4d5 cpu/x86/smm_module_loader.c: Clean up printing the CPU map
There is no reason to do this in a separate loop.

Change-Id: I7fe9f1004597602147aae72f4b754395b6b527cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 10:08:10 +00:00
Michał Żygowski bc749a068a soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding
Some Super I/Os may be strapped to respond on the secondary ports
0x4e/0x4f. Enable them early so that mainboard is able to initialize
a serial port for example.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11 08:48:34 +00:00
Michał Żygowski dccfb8a215 soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for
PCH-S.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11 08:48:15 +00:00
Michał Żygowski f3cc03b137 soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11 08:46:50 +00:00
Michał Żygowski 02315f9217 soc/intel/alderlake: Select FSP2.3 for ADL-S
The FSP available at Intel R&DC kit #1000166 indicates FSP version 2.3
in the FSP headers.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11 08:43:32 +00:00
Michał Żygowski a1636d737c soc/intel/alderlake: Introduce PCH-S symbol
Introduce SOC_INTEL_ALDERLAKE_PCH_S symbol to differentiate from the
low power chipsets.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I47676723747458b8b7fe726e900843c198901bda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11 08:42:29 +00:00
Subrata Banik 88381c9480 soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
This patch binds all FSP-M and FSP-S UPDs required for serial
redirection with `FSP_ENABLE_SERIAL_DEBUG` config to allow coreboot to
choose when to enable FSP debug output redirection to serial port.
For example:
PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S
SerialDebugMrcLevel => For controllig MRC debug level.

With this change FSP debug output will only be enabled when the user
enables `FSP_ENABLE_SERIAL_DEBUG` from site-local config with coreboot
serial image.

BUG=b:225544587
TEST=Able to build and boot brya. Also, the FSP debug log is exactly
the same before and with this code change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63167
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-11 06:16:59 +00:00
Subrata Banik 9bc5b0097b drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
Commit 3ba6f8cdf (drivers/intel/fsp2_0: Add native implementation for
FSP Debug Handler) implements a native FSP debug handler.

However, coreboot still can't control when to redirect FSP debug
output to the serial console, i.e., at present, integrating a FSP debug
binary is enough to output FSP serial messages irrespective of whether
user is intended to see FSP debug log.

coreboot needs additional mechanism to control FSP debug binary to
redirect debug messages over serial port. This patch introduces a
config `FSP_ENABLE_SERIAL_DEBUG` to control the FSP debug output, user
to enable this config from site-local config file in case like to override
the default FSP serial redirection behaviour in more controlled way from
coreboot.

There could be scenarios as below:

Scenario 1: coreboot release image integrated with the FSP debug
binaries, is capable of redirecting to the serial console, but coreboot
decides to override the config as below to skip FSP debug output
redirection to the serial port.

     `#`FSP Serial console disabled by default (do not remove)
     `#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set

Scenario 2: For coreboot serial image with FSP debug binaries integrated
but coreboot decides to skip FSP debug output redirection to the serial
port.

     `#`FSP Serial console disabled by default (do not remove)
     `#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set
        CONFIG_CONSOLE_SERIAL=y
        CONFIG_CONSOLE_SERIAL_115200=y
        CONFIG_UART_DEBUG=y
        CONFIG_UART_FOR_CONSOLE=0

Scenario 3: The final image could be a coreboot serial image with FSP
serial redirection enabled to output to the serial port.

        CONFIG_FSP_ENABLE_SERIAL_DEBUG=y
        CONFIG_CONSOLE_SERIAL=y
        CONFIG_CONSOLE_SERIAL_115200=y
        CONFIG_UART_DEBUG=y
        CONFIG_UART_FOR_CONSOLE=0

BUG=b:227151510
TEST=Able to build and boot google/redrix with all scenarios between #1--#3
and able to meet the expectation as mentioned above.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11 06:15:52 +00:00
Angel Pons 9d8dac0dbe nb/intel/sandybridge: Restore `mainboard_early_init()` call
Commit 7a87433091 (mb/google,samsung: Drop
init_bootmode_straps()) got rid of the `mainboard_early_init()` function
call and weak definition in Sandy Bridge code. However, this function is
still used by several Sandy Bridge mainboards, so bring back the dropped
call and weak definition.

The aforementioned commit did not cause any build-time errors because it
did not remove the `mainboard_early_init()` function declaration.

Change-Id: I82768e9a187696d42b61be44d4aa048acc19d551
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-10 08:47:57 +00:00
Kyösti Mälkki 7a87433091 mb/google,samsung: Drop init_bootmode_straps()
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-09 02:50:01 +00:00
Frans Hendriks 5619ea2b98 src/mb/facebook/fbg1701: Verify FSP and SPD binaries in bootblock
romstage uses FSP and SPD before these are verified.

Verify the FSP and SPD binaries in bootblock and measure these in
romstage.

BUG=N/A
TEST=Boot Facebook FBG1701 and check log for FSP and SPD verified in
bootblock.

Change-Id: I061affa5111fb14d69a8459575e0c72f71b1a1aa
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63446
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-08 14:45:14 +00:00
Frans Hendriks a02b77a96b IASL: Correct warning message for IASL missing dependency
Warning for _SRS includes _SRS.
Warning for _DIS includes must have _SRS twice.

Remove requirement _SRS for _SRS is present.
Removed second _SRS for _DIS is present.

BUG=N/A
TEST=Verify correct message on built of facebook FBG1701

Change-Id: I1be740354b159e931e41323aef14e160cc09af19
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>´
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63250
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-08 14:44:31 +00:00
Werner Zeh f2234422e9 soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameter
Commit 1a4496e79f (soc/{apl,glk}: Allow to select the primary graphics
device) adds code to set the FSP parameter 'PrimaryVideoAdaptor' based
on the enum description of the FspmUpd.h for Apollo Lake.

Unfortunately, the comment in the header file does not match the
implementation in the FSP and hence setting PrimaryVideoAdaptor to
'GPU_PRIMARY_IGD' will be treated as if the selection was
'GPU_PRIMARY_PCI'. This in turn leads to Linux gfx driver issues for
earlier driver implementations.

This commit corrects the enum values for the FSP parameter to match the
implementation.

TEST=Boot into Linux on mc_apl1 and verify that graphics works.

Change-Id: Iedbc144fa809f6d4587f5223b235ee95579c48f7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-08 14:43:45 +00:00
Subrata Banik 01bf0020d2 soc/intel/common/cse: Show CSE device slot and function number properly
This patch fixes a problem where the `is_cse_devfn_visible` function is
unable to show the CSE device slot and function number properly. 

BUG=b:211954778
TEST=Able to display CSE device slot and function number properly as
below:

Before:
[DEBUG]  PCI: 00:16.0 final
[WARN ]  HECI: CSE device 00.0 is disabled
[WARN ]  HECI: CSE device 00.0 is disabled
[WARN ]  HECI: CSE device 00.0 is disabled
[WARN ]  HECI: CSE device 00.0 is disabled
[WARN ]  HECI: CSE device 00.0 is disabled

With this code changes:
[DEBUG]  PCI: 00:16.0 final
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76a634c64af26fc0ac24e2c0bb3a8f397a65d77b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-08 14:42:27 +00:00
Subrata Banik 96527da2da soc/intel/cse: Allow calling all functions associated with `cse_final`
This patch fixes a problem where `cse_final` only calls into 1 function
from available `notify_func` lists.

BUG=b:211954778
TEST=Able to execute `cse_final_end_of_firmware` function as part of
`cse_final` call.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I04d8c9c1213ddeb9ed85473e62fcca298c0d5172
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-08 14:42:00 +00:00
Joey Peng c0c40b94e3 mb/google/brya/var/taniks: Enable Genesys L1 max entry delay
The workaround causes the eMMC controller to not enter its L1
during the boot process

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 20:48:18 +00:00
Sridhar Siricilla 52479c7919 soc/intel/common: Update CSE sub partition update
The patch adds support in the CSE Sub partition update procedure
to use GET_BOOT_PARTITION_INFO HECI command output to create the
region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO
HECI command provides CSE's RO and RW boot partition information.

Existing code relies on FMD file to get the CSE's boot partition's
(CSE RO and CSE RW) start and size details. This change make
independent of FMD file declaration with respect to CSE RO and CSE RW.

TEST=Build and verify the CSE RO and CSE RW region device information
through code instrumentation. Also, did boot test on Kano system.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 20:48:03 +00:00
Felix Held 6e296b3773 MAINTAINERS: lower maintenance level of super I/O and superiotool
I don't really get around to review super I/O or superiotool patches any
more, so lower the maintenance level of those. If anyone else wants to
step up as new maintainer for those two, feel free to do so.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id7bd3c68c1adc0db82dab078291918742b453d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-07 20:40:52 +00:00
Kyösti Mälkki 4ff218aa71 ChromeOS: Add DECLARE_x_CROS_GPIOS()
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 20:38:12 +00:00
Akihiko Odaki f0be9e3472 ec/google/chromeec: Initialize device_path subid
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Change-Id: I910998a5555319cf9840493a31df4934054e08ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 16:20:59 +00:00
Lean Sheng Tan e8df93af91 soc/intel/alderlake: Hook up PAVP to Kconfig
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for
multimedia content) to Kconfig.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-07 16:20:21 +00:00
Lean Sheng Tan 4b45d4c802 soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
The FSP needs to program VrPowerDeliverDesign configuration per
platform according to the platform capabilities to avoid incorrect
electrial/power parameters. This value is an enum of the available
power delivery segments that are defined in the Platform Design
Guide.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I74859e6735e59a15084a9e690b43f68341862833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 16:19:56 +00:00
Teddy Shih 369b9ad787 mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption
To achieve low power consumption, we disable unused PCIe and SATA
pins at beadrix/overridetree.cb according to baseboard/devicetree.cb
and mainboard schematic. Original measured beadrix board's power
consumption is about 250 mW. After we disable unused PCIe and SATA
pins, as well as, enable the other low power MUX CL (3487086: USB
MUX: Update low power mode of MUX anx7447 used as MUX only |
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/
+/3487086), the measured power consumption achieves about 110 ~ 116
mW, as well as, meets Google battery life for 14 days in the suspend
state and Intel low power consumption about 116 mW.

BRANCH=dedede
BUG=b:204882915
TEST=on beadrix, measured power consumption meets Intel power
consumption.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776
Reviewed-by: Teddy Shih <teddyshihau@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07 15:31:57 +00:00
Kenneth Chan 0fd3c38d84 mb/google/guybrush: allow MKBP devices and disable TBMC device
Enable MKBP (Matrix Keyboard Protocol) interface for all guybrush family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.

BUG=b:227240985
BRANCH=guybrush
TEST=manual test on Dewatt:
     Volume Up/Down and Power buttons, Tablet Mode switch

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63394
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07 15:28:40 +00:00
Jeff Daly 380fcfb39d soc/intel/denverton_ns/chip.c: add soc_acpi_name function
Intel common SoC code uses SoC-specific soc_acpi_name function to
generate ACPI tables, add this to Denverton

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I5f50733656ca7724caf8a6570bcb21f7b761c3ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-04-07 14:44:44 +00:00
Jeff Daly dc5d3f368b soc/intel/denverton_ns: add common device function macros
Add device function macros for Denverton similar to other SoCs

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I75daaf4907515f80a10c003eb473bbe557a42acc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-04-07 14:44:06 +00:00
Rex-BC Chen 29cad5a59e soc/mediatek/mt8186: Disable unused power
To save the power consumption, we disable the unused power of
optional components in coreboot.

BUG=none
TEST=the value of power consumption is as expected.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-04-07 14:43:36 +00:00
Arthur Heymans a552cfc981 drivers/amd/agesa/romstage.c: Move timestamp and console init up
Follow-up commits move this to a common place.

Change-Id: I26a37f9384a581a8a750efccc2100a5c6a6f0f85
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-07 10:59:29 +00:00
Reka Norman 1a8ecb6438 mb/google/brya/var/nereid: Add WLAN power sequence
There are currently two issues related to the WLAN power sequencing on
nereid:
- If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck
  in S3.
- During warm reboot, if we only assert RST without pulling the power
  low, then the kernel crashes.

As a workaround while we investigate these issues, we pull the EN high
in S5, then actively drive it low in bootblock and high in romstage to
make sure it goes low during warm reboot.

BUG=b:227694137, b:225261075
TEST=Cold boot succeeds, and there's no kernel crash during warm reboot.

Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07 08:15:14 +00:00
Reka Norman 07bb783c4b mb/google/brya/var/nereid: Enable pen garage
BUG=None
TEST=evtest works:
Select the device event number [0-14]: 9
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
  Event type 0 (EV_SYN)
  Event type 5 (EV_SW)
    Event code 15 (SW_PEN_INSERTED) state 1
Properties:
Testing ... (interrupt to exit)
Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649153020.275201, -------------- SYN_REPORT ------------
Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1649153025.848689, -------------- SYN_REPORT ------------
Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649153028.383195, -------------- SYN_REPORT ------------
Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1649153080.869155, -------------- SYN_REPORT ------------

Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-07 08:14:58 +00:00
Reka Norman a6de947a6b mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI
Some bytes in the descriptor need to be set differently for Type-C and
HDMI. To allow using a single firmware variant for both cases, update
the descriptor at runtime based on fw_config. This is a temporary
workaround while we find a better solution.

The byte values were determined by changing the following CSE strap and
comparing the generated descriptors:
Type-C: TypeCPort2Config = "No Thunderbolt"
HDMI:   TypeCPort2Config = "DP Fixed Connection"

The default value before updating the descriptor is Type-C, but this was
chosen arbitrarily.

BUG=b:226848617
TEST=Type-C and HDMI both work on nereid with fw_config set correctly.

Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07 08:14:37 +00:00
Reka Norman e790f929bd soc/intel/alderlake: Add support to update descriptor at runtime
On nereid, we need to update the descriptor based on fw_config (see
the follow-up patch), so add support to update the descriptor at
runtime. This is a temporary workaround while we find a better solution.

This is basically adding back the configure_pmc_descriptor() function
removed in CB:63339, just making it generic and allowing it to update
multiple bytes at once.

BUG=b:226848617
TEST=With the following patch, Type-C and HDMI work on nereid.

Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07 08:12:20 +00:00
Sridhar Siricilla d7cdeee74d soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
The patch removes Kconfig CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
code which updates PMC descriptor for an intermediate ADL-P SoC
stepping A0. Since intermediate ADL-P SoC is no longer supported and no
board is selecting the Kconfig, so remove the code that updates PMC
descriptor.

TEST=Build and boot Gimble board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63339
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07 08:11:43 +00:00
Kyösti Mälkki 662353ac3e ELOG: Refactor watchdog_tombstone
The symbol watchdog_tombstone is not really about ChromeOS
but ELOG instead. This prepares for furher move of the
watchdog_tombstone implementation.

Change-Id: I8446fa1a395b2d17912a23b87b83277c80828874
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-06 23:42:56 +00:00
Arthur Heymans 24a20e4d21 mb/ti/beaglebone/board.fmd: Use 'FLASH' as device name
FLASH is often used when accessing FMAP base and size from
fmap_config.h so it's handy to be consistent with all other boards.

Change-Id: Ibba938c72d42ac74dcea8e8e6478ddae510d8c03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 23:10:06 +00:00
Chris.Wang ec7a932aa2 mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
Setting the clock source depends on clock request pin for WLAN/SD/SSD
device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim,
clock source 0/1/2 are routed for WLAN/SD/SSD device.

BUG=b:227297986
BRANCH=none
TEST=Build

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-06 17:41:41 +00:00
Kyösti Mälkki 4fdd84e716 ChromeOS: Promote variant_cros_gpio()
The only purpose of mainboard_chromeos_acpi_generate()
was to pass cros_gpio array for ACPI \\OIPG package
generation.

Promote variant_cros_gpio() from baseboards to ChromeOS
declaration.

Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06 17:40:50 +00:00
Sridhar Siricilla afe5562ca3 soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake
and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h
for Comet Lake, Jasper Lake and Tiger Lake SoCs.

TEST=Build code for Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06 17:34:25 +00:00
Sridhar Siricilla fad76f33a9 mb/google/brya: Enable dynamic debug capability for brya family
The patch enables dynamic debug capability for Brya family of boards.

BRANCH=MAIN
BUG=b:153410586
TEST= Verified the CSE firmware update functionality on Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-04-06 17:34:11 +00:00
Sridhar Siricilla f5e94b6e72 soc/intel/alderlake: Enable debug driver for Alder Lake platform
The patch enables dynamic debug capability driver for Alder Lake
platform.

BUG=b:153410586
TEST= Build code for Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic4df3d7f3d6585bd37c632b1a3f0a47c94b63697
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06 17:33:54 +00:00
Sridhar Siricilla 2c2706ccef soc/intel/common: Add support to control coreboot and Intel SoC features
The patch adds a framework to control coreboot and Intel SoC features
dynamically. BIOS reads control information from OEM Section in the
Descriptor Region and control the developer selected features.
With the feature, debug team can control the selected SoC and coreboot
features without rebuilding coreboot.

In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has
to be selcted from mainboard.

The OEM section starts from offset:0xf00 till end of the Descriptor
Region(0xfff).

BUG=b:153410586
BRANCH=None
TEST=Verified CSE firmware update functionality on brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-04-06 17:32:31 +00:00