Commit Graph

47527 Commits

Author SHA1 Message Date
Michał Kopeć bd656b4e4c superiotool/ite: add IT8625E EC registers
Add support for dumping ITE IT8625E Environmental Controller registers.

Values as per "IT8625E Preliminary Specification V0.3 (For D Version)".

Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-06 16:28:53 +00:00
Sean Rhodes 36b6e79f1c ec/starlabs/merlin: Add EC related files for Cezanne boards
Add EC memory layout and Q events for AMD Cezanne based boards, "Byte"
and "Fighter", which both use the ITE 5570E.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-06 16:21:31 +00:00
Sean Rhodes e8b090c509 ec/starlabs/merlin: Correct Q event for CPU DN SPEED
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieea1c8d0923f6ea6b13cf76525c9c4c686a92c40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 16:21:03 +00:00
Sean Rhodes f03c372a6e mb/starlabs/labtop: Remove subsystem device ID
Remove the subsystem device ID for HDA devices, so that the correct
Intel [8086:xxxx] is used. This was an old workaround for Windows
that is no longer required with a new driver.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 16:20:51 +00:00
Uwe Poeche e9b417c0a0 soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree
This patch provides the set value for intel speed step in devicetree
for FSPS. Before that in case of not set value in device tree the
default value of disabled was overwritten by default enabled of FSP.

Test: mainboard/siemens/mc_ehl/variants/mc_ehl1
Check status of Bit 16 in MSR 0x1a0 after boot.

Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 16:20:27 +00:00
Arthur Heymans ca74d7e65b drivers/intel/fsp1_1: Rename hob finding functions
The hob finding functions are never looped over so there is no point
for the 'next' inside their name.

Change-Id: I18e452d313612ba14edda479d43f2797f6c84034
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 16:20:06 +00:00
John 2bcc5f39c1 soc/intel/common: Add IOE SBI access for TCSS functions
Meteor Lake has the IOE Die for TCSS. This change adds IOE SBI access
for TCSS pad configuration and Thunderbolt authentication.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06 16:19:36 +00:00
John 848b42558c soc/intel/common: Abstract the common TCSS functions
This change abstracts the common TCSS functions for pad configuration
and Thunderbolt authentication.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06 16:19:18 +00:00
Kyösti Mälkki 740eee5eec ChromeOS: Drop filling ECFW_RW/RO state in CNVS
This field was never meant to be filled out by coreboot, because it
can't know what the right value for this will be by the time the OS
is running, so anything coreboot could fill in here is premature.

This field is only read by the chromeos-specific `crossystem` utility,
not by kernel code, so if one does not run through depthcharge there'll
be many more broken assumptions in CNVS anyway.

Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06 09:31:25 +00:00
Kyösti Mälkki e50bb8fc9e ChromeOS: Add legacy mainboard_ec_running_ro()
Motivation is to have mainboard_chromeos_acpi_generate()
do nothing else than fill ACPI \OIPG package.

Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-06 09:21:46 +00:00
Zheng Bao 487d04540b amdfwtool: Add a macro to set explicitly second gen for old SOCs
It is more reasonable than getting the value from memset.

For the reserved bits, keep them as they were for old SOCs.

Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-05 17:45:58 +00:00
Chris.Wang ac43324211 mb/google/guybrush/var/dewatt: Correct samsung part number value in SPD data
The value at offset 329 should be:
0x4B -> "K" not 0x48 -> "H" in ASCII code.

BUG=b:224884904
TEST=Build, confirm the part number is matched the corresponding parts

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05 16:45:49 +00:00
Robert Zieba 39e6cc5981 mb/google/guybrush/var/dewatt: Override SPD file for Samsung parts
K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This
commit overrides the default SPD files used for these parts

BUG=b:224884904
TEST=Verified that Dewatt SKU1 and SKU3 boot with changes

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05 14:51:32 +00:00
Robert Zieba 255b1fb38b util/spd_tools: Add ability to override SPD file for parts
This commit adds the ability to override the SPD file that is used for a
specific part.

BUG=b:224884904
TEST=Verified that generated makefile uses specified SPD file and that
it remains unchanged when this capability is not used

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05 14:50:56 +00:00
Varshit B Pandya be1a050772 soc/intel/alderlake: Add HID for DPTF Battery Participant
HID is defined in Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817)

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check BAT1 device HID

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-04-05 14:49:07 +00:00
Varshit B Pandya 170a76caa7 drivers/intel/dptf: Add support for Battery participant
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add
support for TBAT device under \_SB.DPTF

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TBAT device

Device (TBAT)
{
    Name (_HID, "INTC1061")  // _HID: Hardware ID
    Name (_UID, "TBAT")  // _UID: Unique ID
    Name (_STR, "Battery Participant")  // _STR: Description String
    Name (PTYP, 0xC)
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
        Return (0x0F)
    }
}

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-04-05 14:48:47 +00:00
Angel Pons 1e124b94fc drivers/wifi/generic/acpi.c: NULL-check pointers before dereferencing
Checking whether a pointer is NULL after it has been dereferenced makes
zero sense. Make sure the `wifi_ssdt_write_properties()` function never
gets invoked with a NULL argument for the `dev` parameter, and simplify
the logic around the `is_cnvi_ddr_rfim_enabled` variable accordingly.

Change-Id: I3fbc9565e7e9b4e1c14a68f6a5fd779577045236
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-04 23:56:15 +00:00
Sean Rhodes 32ec4526a0 ec/starlabs/merlin: Remove comment about OPWE
OPWE offset didn't exist, but it does now so remove the comment about
this.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4a1310c779002dfb00d01a22437ea223bb406609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04 21:54:45 +00:00
Sean Rhodes 32528976ff mb/starlabs/lite: Add Lite Mk IV variant
Tested using upstream edk2:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/starlite-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04 21:54:24 +00:00
Frans Hendriks ae2b79037f src/mb/facebook/monolith: Remove IGNORE_IASL_MISSING_DEPENDENCY
CB:63244 solved the missing dependency on _PRS

The config IGNORE_IASL_MISSING_DEPENDENCY can be removed.

BUG=N/A
TEST=build facebook monolith and verify no IASL warning is reported.

Change-Id: I0d7c99e69d56aa8ebe08b52c91ef800390263185
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63245
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04 19:09:15 +00:00
Frans Hendriks 9cd9f38c4b src/mb/facebook/monolith/acpi/superio.asl: Remove _PRS
IASL reports warning on missing _SRS.

Devices have fixed configuration which is always enabled.
Remove _PRS for this fixed configuration.

BUG=N/A
TEST=built facebook monolith and verify no IASL warning is reported.

Change-Id: I554d3497255c1e50cdbe74b1cffc9f2c59fbae77
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04 19:08:59 +00:00
Damien Zammit 3605dac10b mb/hp/z220_series: Convert z220_sff_workstation into variant
No functional change, just refactoring to make room for CMT variant.

Built with BUILD_TIMELESS=1 and no config included before and after.
	$ diff master.rom build/coreboot.rom
	$

TESTED: boots to SeaBIOS on HP Z220 SFF

Flashed bios region internally, mainboard also has FDO
(flash descriptor override) jumper that allows r/w to whole flash.

Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04 19:08:02 +00:00
Lean Sheng Tan 311ddf3b81 soc/intel/alderlake: Add new CPU ID
Add new CPU ID 0x906A3 (L0 stepping).

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63302
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04 17:49:17 +00:00
Lean Sheng Tan 9e78dd1357 soc/intel/alderlake: Update CPU IDs with correct steppings
Update ADL CPU IDs per correct steppings listed in Intel Doc 626774.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04 17:48:56 +00:00
Frans Hendriks 74d6efc924 src/mb/portwell/m107: Remove IGNORE_IASL_MISSING_DEPENDENCY
CB:63248 solves the missing dependency on _PRS

The config IGNORE_IASL_MISSING_DEPENDENCY can be removed.

BUG=N/A
TEST=Build portwell M107

Change-Id: I2ed9fdd541ba9431e59364a42dd03f60b54b6720
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63249
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04 13:55:30 +00:00
Frans Hendriks da7a22f49e src/mb/portwell/m107/acpi/superio.asl: Remove _PRS
IASL reports warning on missing _SRS.

Device has fixed configuration which is always enabled.
Remove _PRS for this fixed configuration.

BUG=N/A
TEST=build portwell m107

Change-Id: Idbc0a67136326c9231c168bfd8fadd2539da6745
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63248
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04 13:55:15 +00:00
Elyes Haouas 9a8d0a03db crossgcc: Upgrade IASL from 20211217 to 20220331
"REDUNDANT_OFFSET_REMARK" to ignore redundant offset remarks is
not needed any more as it’s included upstream.

Changes: https://acpica.org/node/199

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-04 13:54:49 +00:00
Elyes Haouas 6d976919d0 crossgcc: Upgrade CMake from 3.22.2 to 3.23.0
Release Notes:
  https://cmake.org/cmake/help/v3.23/release/3.23.html

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib31124baa3cae65211ad361a7d41c9504105be91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-04 13:54:20 +00:00
Eddy Lu 15a33fd1bf mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHz
Tune I2C parameters to make sure I2C1 and I2C7 bus speed is around 1MHz.

BUG=b:207333035
BRANCH=none
TEST=built and verified adjusted I2C speed around 1MHz

Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff
Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63241
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04 13:53:38 +00:00
Felix Held c6b71bc614 soc/amd/cezanne/fw.cfg: provide default SPL table binary
Chause doesn't get to x86 bootblock without the SPL table binary in the
PSP directory table, so I assume that Majolica won't get to x86
bootblock either, since the Cezanne SoC default is not to include any
SPL table binary. This was caused by a combination of
commit 6c5ec8e31c (amdfwtool: Add options
to support mainboard specific SPL table) that caused a regression in
amdfwtool and commit c5b912f788
(soc/amd/cezanne: Allow to specify SPL table path in Kconfig) that
removed the default for the Cezanne SoC. Fix this by adding the default
SPL table file back to the fw.cfg file which will get ignored by
amdfwtool when a mainboard selects SPL_TABLE_FILE and specifies another
SPL table binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-03 17:07:08 +00:00
Felix Held 11b0d360ba util/amdfwtool/data_parse: fix SPL table handling regression
Use the SPL table binary from the config file if no override is
specified via the spl-table command line argument. This fixes a
regression caused by commit 6c5ec8e31c
(amdfwtool: Add options to support mainboard specific SPL table).

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-03 17:06:48 +00:00
Paul Fagerburg ac68384c0c util/cbmem: add type cast
arch_convert_raw_ts_entry returns a uint64_t, which needs to be cast
on ARM systems to avoid a type error.

BUG=b/227871959
TEST=no build errors in downstream

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I87a83758b7f122b77f9631c669c7cd8df66f8d1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63317
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02 16:12:28 +00:00
Subrata Banik def18c4068 soc/intel/common/block/fast_spi: Refactor ROM caching implementation
This patch removes different implementation to cache the SPI ROM between
early and later boot stage where SPI ROM caching doesn't need even
advanced implementation like `mtrr_use_temp_range()` as SPI ROM ranage
is always mapped to below 4GB hence, simple `set_var_mtrr()` function
can be sufficient without any additional complexity.

BUG=b:225766934
TEST=Calling into `fast_spi_cache_bios_region()` from ramstage is able
to update the temporary variable range MTRRs and showed ~44ms of boot
time savings as below:

Before:
  90:starting to load payload                    1,084,052 (14)
  15:starting LZMA decompress (ignore for x86)   1,084,121 (68)
  16:finished LZMA decompress (ignore for x86)   1,140,742 (56,620)

After:
  90:starting to load payload                    1,090,433 (14)
  15:starting LZMA decompress (ignore for x86)   1,090,650 (217)
  16:finished LZMA decompress (ignore for x86)   1,102,896 (12,245)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I43973b45dc6d032cfcc920eeb36b37fe027e6e8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63221
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02 15:00:55 +00:00
Subrata Banik 1f09a2ac81 cpu/x86/mtrr: Delay removing `temp` variable range MTRR snapshot
This patch delays removing `temporary` MTRR snapshots to avoid conflicts
with other operations attached with same `BS_PAYLOAD_BOOT/BS_ON_EXIT`
boot state.

BUG=b:225766934
TEST=Having variable MTRR snapshot using display_mtrrs() is able to
list only the permanent MTRRs and all temporary MTRRs are removed
prior to boot to payload.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I602dca989745159d013d6573191861b296f5d3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-02 15:00:24 +00:00
Subrata Banik 7578ea43ce {cpu/x86, drivers/amd}: Use `get_var_mtrr_count()` to get MTRR count
This patch replaces the implementation that is used to get the number of
variable MTRRs with `get_var_mtrr_count()` function.

BUG=b:225766934
TEST=Able to build and boot google/redrix board to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4751add9c45374e60b7a425df87d06f52e6fcb8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-02 14:55:24 +00:00
Subrata Banik 3ad00d0c89 cpu/x86/mtrr: Make useful MTRR functions available for all boot stages
This patch migrates a few useful MTRR functions as below from
`earlymtrr.c` file to newly created common stage file `mtrrlib.c`.
1. get_free_var_mtrr
2. set_var_mtrr
3. clear_all_var_mtrr

These functions can be used to perform the MTRR programming from IA
common code SPI driver as `fast_spi.c` without requiring two separate
implementations for early boot stage (till romstage) and for ramstage
onwards.

BUG=b:225766934
TEST=Able to build and boot google/redrix board to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2c62a04a36d3169545c3128b4231992ad9b3699d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-02 14:53:00 +00:00
Subrata Banik 6de1d9ff4e drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp
from FPDT (Firmware Performance Data Table) and display right after
FSP-S exits (from `fsp_silicon_init()` function), based on SoC user
selects the required `DISPLAY_FSP_TIMESTAMPS` config.

The prerequisite to this implementation is to have FSP binary built with
`PcdFspPerformanceEnable` PCD set to `TRUE` to allow FSP to populate
the FPDT HOB.

BUG=b:216635831
TEST=Able to dump FSP performance data with DISPLAY_FSP_TIMESTAMPS
Kconfig selected and met the FSP prerequisites.
+--------------------------------------------------+
|------ FSP Performance Timestamp Table Dump ------|
+--------------------------------------------------+
| Perf-ID	Timestamp(ms)	       String/GUID |
+--------------------------------------------------+
    0	          460253    SEC/52c05b14-0b98-496c-bc3b04b50211d680
   50	          460263    PEI/52c05b14-0b98-496c-bc3b04b50211d680
   40	          460274    PreMem/52c05b14-0b98-496c-bc3b04b50211d680
    1	          495803    9b3ada4f-ae56-4c24-8deaf03b7558ae50
    2	          508959    9b3ada4f-ae56-4c24-8deaf03b7558ae50
    1	          515253    6141e486-7543-4f1a-a579ff532ed78e75
    2	          525453    6141e486-7543-4f1a-a579ff532ed78e75
    1	          532059    baeb5bee-5b33-480a-8ab7b29c85e7ceab
    2	          546806    baeb5bee-5b33-480a-8ab7b29c85e7ceab
    1	          553302    1b04374d-fa9c-420f-ac62fee6d45e8443
    2	          563859    1b04374d-fa9c-420f-ac62fee6d45e8443
    1	          569955    88c17e54-ebfe-4531-a992581029f58126
    2	          575753    88c17e54-ebfe-4531-a992581029f58126
    1	          582099    a8499e65-a6f6-48b0-96db45c266030d83
 50f0	          599599    unknown name/3112356f-cc77-4e82-86d53e25ee8192a4
 50f1	          716649    unknown name/3112356f-cc77-4e82-86d53e25ee8192a4
    2	          728507    a8499e65-a6f6-48b0-96db45c266030d83
    1	          734755    9e1cc850-6731-4848-87526673c7005eee
....

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-04-02 14:52:24 +00:00
Karthikeyan Ramasubramanian 9842bef525 mb/google/skyrim: Fix ESPI communication issues
* Use dedicated ALERT pin to resolve NO_RESPONSE error/status while
getting target configuration.
* Configure the ESPI to operate at 16 MHZ since operating at 33 MHz
causes boot stall.

BUG=b:226635441
TEST=Build and Boot to OS in Skyrim. Ensure that EC <-> AP communication
is working fine through Host Command debug logs in EC console, ectool
version command.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I951afdada8ee4f917cdeba8e287e5a2ae77c97ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63286
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02 14:50:28 +00:00
Shelley Chen faaa759763 herobrine: fix emmc and sd card clocks
Found an issue where emmc and sd clocks were being misconfigured due
to using incorrect integer values when called instead of the defined
enums.  Fixing by splitting the clock_configure_sdcc() function into
two (sdcc1 and sdcc2) as there was no commonality between the two
cases anyway.  As a result, we can also get rid of the clk_sdcc enum.

BUG=b:198627043
BRANCH=None
TEST=build herobrine image and test in conjunction with CB:63289
     make sure assert is not thrown.

Change-Id: I68f9167499ede057922135623a4b04202f4da9b5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-02 07:24:01 +00:00
Angel Pons 0b7aa5abcb mb/dell/snb_ivb_workstations: Choose correct PCH for OptiPlex 9010
The Dell OptiPlex 9010 uses a Q77 PCH, which is Panther Point. The only
difference is the definition of the `CROS_GPIO_DEVICE_NAME` macro, which
is not used for non-ChromeOS coreboot builds.

Change-Id: I7ad07b464aef24f7749c3fe9300b7f7dd865e47b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-04-01 22:22:48 +00:00
Angel Pons caa3b530e6 mb/dell/snb_ivb_workstations: Fix SMBIOS slot desc for PCH PCIe ports
The PCH's PCIe ports do not support Gen3 speeds, only Gen1/Gen2.

Change-Id: I7df61af1953ec99000c6c501b017e553190a46b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-04-01 22:22:24 +00:00
Sean Rhodes 352ef9f51c mb/starlabs/labtop: Disable legacy_8254_timer by default
It was enabled due to known compatibility issues with Qubes OS.
Since the release of R4.1.0, this issue is no longer present so
it can be disabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iab6048dc93112b9365f0c2b46225569073eb32f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-04-01 22:21:31 +00:00
Rob Barnes b7840ed815 mb/google/guybrush: Remove elog_gsmi_cb_mainboard_log_wake_source
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes
eSPI transactions. If the SMI interrupts an ongoing eSPI transaction
from the OS it will conflict and cause failures. Removing this call to
avoid conflicts. This can be re-enabled after refactoring
google_chromeec_get_mask to use ACPI MMIO.

BUG=b:227163985
BRANCH=gubyrush
TEST=No 164 errors detected during suspend_stress_test
/sys/firmware/log output after resume before change:
SMI# #1
ELOG: Event(B0) added with size 9 at 2022-03-31 19:52:51 UTC
GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000
ELOG: Event(9F) added with size 14 at 2022-03-31 19:52:51 UTC
Chrome EC: clear events_b mask to 0x0000000000000000
after change:
SMI# #6
ELOG: Event(B0) added with size 9 at 2022-03-31 19:50:19 UTC
GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000
ELOG: Event(9F) added with size 14 at 2022-03-31 19:50:19 UTC

Change-Id: I3320e3fb8bd9e9e0db84332e1d147a0af25f7601
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63280
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 22:20:53 +00:00
Stephen Edworthy 66d94ba4c0 mb/starlabs/laptop: Enable rtd3 for SSD on TGL
Enabling rtd3 reduces power consumption when the SSD is idle.

Tested and verified on the StarBook Mk V (TGL), using PowerTop
on Manjaro 21.2.5 GNOME at 20% Brightness.

Signed-off-by: Stephen Edworthy <stephen@starlabs.systems>
Change-Id: I0d8aa185a322bb8d1aba51ccaab03c521cec2770
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-04-01 22:20:03 +00:00
Reka Norman a6fd7105e8 mb/google/brya/var/nereid: Add separate VBT for HDMI
BUG=b:226848617
TEST=HDMI works on nereid

Cq-Depend: chrome-internal:4650256
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I6a90d3d86b32f73ec0130e582539d1c5b045da62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01 22:19:27 +00:00
Reka Norman cb51189897 mb/google/brya/var/nereid: Disable C1 PMC mux conn for HDMI
BUG=b:226848617
TEST=HDMI works on nereid

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I039c30f95d959dba489b24b6938d08da937c5e03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01 22:19:10 +00:00
Reka Norman e78669e7fc soc/intel/common/tcss: Check conn device enabled in tcss_get_port_info
BUG=b:226848617
TEST=With the following change, the nereid C1 PMC mux conn is disabled
based on fw_config, allowing HDMI to work.

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I487f3ca4be4ead0c5dfb46e9eb19de5ae9b9bda9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63237
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 22:18:54 +00:00
Sean Rhodes c0646fc910 mb/starlabs/labtop: Add CMOS defaults for EC functions
Set the CMOS defaults for EC related functions:
* Function Lock = Enabled
* Trackpad = Enabled
* Keyboard Backlight Brightness = Off
* Keyboard Backlight State = Enabled

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I528c30893d2af87584a09f23b982b5f36b37a873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-01 22:18:20 +00:00
Matt DeVillier 190086e664 device/i2c_bus: Constify i2c_busdev and i2c_link
Change-Id: If795087ecdaea24ad7834dcc6d5bf6a72f2aea8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-01 22:17:58 +00:00
Karthikeyan Ramasubramanian 77c1f5c035 mb/google/skyrim/var/skyrim: Add ELAN trackpad config
Add support for ELAN trackpad on I2C0 bus.

BUG=None
TEST=Build and boot to OS in Skyrim. Perform evtest on Elan trackpad.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia1522af3f35ef131dda74c4aabecc4fa532dfbec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-01 22:17:37 +00:00