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26792 Commits

Author SHA1 Message Date
Eric Biederman 709850a21b - Ensure every copy of Options.lb uses: 
CROSS_COMPILE
  CC
  HOSTCC
  OBJCOPY


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 10:48:04 +00:00
Eric Biederman d0805e0b55 - Ensure the all target is the first commands in the makefile.... 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 09:03:47 +00:00
Eric Biederman 1c1b858f0f - Put the rule for the Makefile at the bottom of the makefile! 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 08:57:09 +00:00
Eric Biederman c149210462 - In the makefile header get the name of the Makefile correct 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 08:50:54 +00:00
Eric Biederman 0e99655670 - Massage the code to generate the top level Makefile so the 
generated Makefile has correct dependencies and is somewhat complete.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 08:21:05 +00:00
Eric Biederman 41d0fa38af - Modify all of the Opteron motherboards to have a separate logical 
chip for the amdk8/root_complex


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 07:26:56 +00:00
Eric Biederman 8bd555297e - Add a new chip northbridge/amd/amdk8/root_complex 
- Moving the functionality around in northbridge/amd/amdk8/northbridge.c
  to put the pci_domain and the apic bus on the root_complex.
  Everything else remains with the individual northbridges.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 07:04:54 +00:00
Yinghai Lu 7bf1b48bd4 *** empty log message *** 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 03:44:01 +00:00
Stefan Reinauer 3779f6a4cb stepan goes to bed now. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 00:26:31 +00:00
Stefan Reinauer d87ce961f6 - some steps towards cross compile 
- add option to force rebuilds even if they were previously ok
- add option to build on target only
- play around


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-05 00:25:19 +00:00
Li-Ta Lo 9562049df5 reformat 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 23:42:54 +00:00
Yinghai Lu b2d77282e0 debug device added 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 22:36:18 +00:00
Li-Ta Lo 652ae6f533 we decide not to enable BM DAM form them 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 21:48:39 +00:00
Yinghai Lu 8085f032f8 SI Class code check 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 21:00:13 +00:00
Li-Ta Lo 2d2bdd3846 removed #if 0 #endif code 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 20:31:04 +00:00
Li-Ta Lo f84926efca tell people that the segment descriptors are different for ROMCC and 
GCC code.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 18:36:06 +00:00
Li-Ta Lo 1995f1af35 removed the comment in the very beginning of hardwaremain(). I don't 
think it is relevant now.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 18:33:33 +00:00
Eric Biederman 23bc47db17 Add Options.lb to various motherboard ports 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 11:09:12 +00:00
Eric Biederman 018d8dd60f - Update abuild.sh so it will rebuild successfull builds 
- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
  enabled.  All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-04 11:04:33 +00:00
Yinghai Lu 4403f60823 *** empty log message *** 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-03 00:47:40 +00:00
Stefan Reinauer e507c85fe3 This hurts more than it helps. byebye 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-03 00:10:15 +00:00
Stefan Reinauer e4932dc760 get qemu-i386 target building again 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-02 20:33:12 +00:00
Stefan Reinauer c3f3e9abf4 update to new structure 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-02 20:29:30 +00:00
Yinghai Lu bf8bb42d6a *** empty log message *** 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-02 18:05:22 +00:00
Yinghai Lu 3974363f09 *** empty log message *** 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-02 17:46:43 +00:00
Yinghai Lu 9434c1b661 Tyan update for ROM_IMAGE_SIZE > 64K 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-11-02 02:34:28 +00:00
Stefan Reinauer 0979969732 fix solo 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-31 23:03:10 +00:00
Eric Biederman 432aa6a255 - Update console.c to have non-inline versions of functions 
- Add exception.c
  Sorry for not including these ealier.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-30 22:59:35 +00:00
Eric Biederman f8a2dddb57 - To reduce confuse rename the parts of linuxbios bios that run from 
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-30 08:05:41 +00:00
Mark Wilkinson 0afcba7a3d Changes to allow Via/Epia code to be compiled after recent code changes. 
New Files :-
	src/cpu/via/model_centaur/Config.lb
	src/cpu/via/model_centaur/model_centaur_init.c

Updated Files :-
	src/arch/i386/include/arch/smp/mpspec.h
		- make write_smp_table a define for non smp systems
	src/cpu/x86/lapic/lapic_cpu_init.c
		- change possible typo
	src/mainboard/via/epia/Config.lb
	src/mainboard/via/epia/Options.lb

	src/mainboard/via/epia/auto.c
	src/mainboard/via/epia/chip.h
	src/mainboard/via/epia/failover.c
		- updated after recent code changes
	src/northbridge/via/vt8601/chip.h
	src/northbridge/via/vt8601/northbridge.c
	src/northbridge/via/vt8601/raminit.c
		- corrections after recent code changes to allow compiling
	src/southbridge/via/vt8231/chip.h
	src/southbridge/via/vt8231/vt8231.c
		- initial pass to allow compiling after recent code changes.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-29 16:16:43 +00:00
Yinghai Lu 97035448f3 *** empty log message *** 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-28 18:44:38 +00:00
Eric Biederman 79186eaecd - Look for all 8 possible cpus 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-27 18:54:13 +00:00
Stefan Reinauer a58cd524fb some more porting to the merge 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-27 17:27:10 +00:00
Eric Biederman 6e53f50082 sizeram removal/conversion. 
- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-27 08:53:57 +00:00
Yinghai Lu 20fc678d65 spare 4s for restart 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-27 02:12:22 +00:00
Eric Biederman 63f2f721b4 - kill the broken and duplicate 855pm directory. Hopefully I have kept 
the least broken one.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-27 01:58:26 +00:00
Eric Biederman dfde9bb649 - Actually enable the Pentium-M cpus 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-27 01:18:47 +00:00
Eric Biederman 3566b3d545 - Bug fixes to the P-III support 
- Initial Pentium-M support


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-27 01:18:16 +00:00
Yinghai Lu eefdb03898 S2885 winbond Superio all resource set 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-27 00:37:30 +00:00
Yinghai Lu fb198640d8 ops and tsc 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-25 19:55:30 +00:00
Yinghai Lu 9cf950ca5a s2735 minor changes 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-25 19:49:50 +00:00
Ronald G. Minnich 3f637906c4 added file 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-25 16:01:30 +00:00
Ronald G. Minnich 7ae74b40bf from Mark Wilkinson, some fixes. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-25 14:57:24 +00:00
Eric Biederman 8e2847c28e - For now use port 0x80 based delays in for the e7501 memory initialization. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-23 03:00:02 +00:00
Eric Biederman 60216355d2 - With Xeon cpus it seems best to use the tsc calibrated with timer2 as 
the time source.  The apic timer also has a variable time base.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-23 02:47:13 +00:00
Eric Biederman 720a8f57ef - Update e7501 northbridge.c to work in the new structure. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-23 02:32:23 +00:00
Yinghai Lu 8abb054c0e *** empty log message *** 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-23 00:05:22 +00:00
Yinghai Lu 2560dbdd50 for S2735 support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-22 21:33:08 +00:00
Yinghai Lu e99433157b *** empty log message *** 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-22 21:03:26 +00:00
Yinghai Lu 79cf1be9e4 *** empty log message *** 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2004-10-22 18:49:09 +00:00