to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*,
and C-ICH.
All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely
not working with this driver anyway (and there's no chance to support
them reasonably with this driver without ending up in #ifdef hell).
ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar
enough to be supported by that ICH7 driver remains to be seen.
This patch was informally acked by Stefan Reinauer
<stepan@coresystems.de> on IRC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
as we've done with the superiotool and flashrom manpages, too (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pass with toolsets that compile larger images. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Both regular and abuild images have been boot tested successfully.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- SST SST39SF010A
- Winbond W29C011
Tested by me on actual hardware, all operations.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
using block erase d8 as discussed with Peter Stuge
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Build-tested with the kontron/986lcd-m target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This includes an early SMI handler.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE
is set.
- Mask moving bits to 32bit when resources are not supposed above 4G. Linux
does not like this, even though the resource is disabled.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Martin Stecklum <stecky@gmx.net> (both write and erase).
The tests were done on an MSI MS-7065 board, so that's supported now
too (wiki page will be updated).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Untested, but should work just as well as the other *PIIX* southbridges
according to the datasheets.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
They all use a different init sequence than the more modern ITE Super I/Os.
For now we only use 0x370 as config port, but 0x3f0 or 0x3bd would also be
valid. Contrary to other Super I/Os, the config port for these is _not_
hardcoded via hardware, instead it can be programmed by software, i.e.
you get to choose whether you want to use 0x370, 0x3f0, or 0x3bd.
Tested on IT8671F by Uwe Hermann and on IT8770F by Urja Rannikko.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
reg much more often. In my case this reduced the time spent in coreboot
by 1.5 sec!
The timeout values of course aren't changed, only the granularity. Also,
I didn't see any udelay() implementation that looked like it couldn't
cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.)
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
due to integer rounding errors. Previously, the formula was:
speed = 2 * (10000/spd_value)
For spd_value=60 this means speed = 2 * 166 = 332, which is less than
333 and coreboot died saying RAM was incompatible. The new formula is:
speed = 20000 / spd_value
For spd_value=60, speed=333, which is fine.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also use different console messages for copying and uncompressing, like
it's already done in similar code in other places.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
'include util/kconfig/Makefile' must come before certain pattern rules
for compilation of kconfig files, otherwise the build would break
in most situations.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* allow versions of "install" that don't know -D
* install libpayload .config and config.h to the target.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This has been tested on hardware by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, use more readable #defines instead of hardcoded config ports for
PM/PM2 related functions, and simplify them a bit.
Build-tested with the AMD dbm690t target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
replaces it with two queues (input, output) where drivers (serial,
keyboard, video, usb) can attach.
The only things left with #ifdefs are initialization (at some point
the drivers must get a chance to register)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
On faster machines, delta might be more then 32 bits
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
If the system in question does not have a superIO, then a read of
0x64 will return 0xFF and we will loop forever.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Remove a possiblity for evil recusion and fix the function and slot
definition in the PCI search loop
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Make libpayload applications multiboot compatible. Add the
multiboot OS table and grok the loader table, especially the
memory map and the command line. This makes libpayload
applications loadable by GRUB.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Allow the payload to enable a PCI device as a bus master.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Using gcc to compile assembly files lets us use preprocessor
directives.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
specification and local testing.
Also tweak a little bit algorithm for (internal) device ID calculation:
Chips from the W83627HF/F/HG/G family have an ID of 0x52 and a multitude of
revisions (0x1x, 0x3a, 0x41, maybe more), chips from the W83627HF/GF family
have the same device ID but revisions 0xfx.
Please note that the last line of the patch simply fixes the comment
about internal device ID composition (upper half of reg 0x21 is used).
I chose the most conservative way of detecting W83627HF - only if reg
0x21 value matches 0xFx we skip the previous logic and keep using it for
all other revisions.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Uwe Hermann