Commit Graph

49621 Commits

Author SHA1 Message Date
Sen Chu 122b45be6e soc/mediatek/mt8186: Add support for PMIC MT6315
On MT8186T, the big cores are powered on by MT6315 via PMIF. This
patch adds the following changes.
- Add MT6315 settings.
- Configure PMIC PMIF for MT6315.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:56:32 +00:00
Sen Chu 28dceaec71 soc/mediatek: Move SPMI interface configuration to SoC folder
The SPMI interface configuration is SoC-dependent.
- MT8192 and MT8195 are the same.
- MT8186 does not need to implement this.
- MT8188 is different from MT8195, and we will submit another patch to
  fix this.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:53:53 +00:00
Rex-BC Chen 1543252e5f soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig option
For MT8186, PMIF_SPMI mode is the hardware default setting, so we don't
need to configure PMIF SPMI IO pins. Add a config to control that.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68578
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:53:02 +00:00
Rex-BC Chen 6d449e005c soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig option
On MT8186, PMIC interface supports PWRAP and PMIF_SPMI while other
MediaTek SoCs support PMIF_SPMI and PMIF_SPI.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I20efa6d84975d781972af9143c0c7e3a272653e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68577
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:52:42 +00:00
Rex-BC Chen 6ad80f1b81 soc/mediatek/mt8186: Add support for reading CPU ID
MT8186 has two slightly different versions: MT8186G and MT8186T
(turbo version). Add get_cpu_id() to identify different CPUs.

BUG=b:249436110
TEST=cpu id is correct.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0612dd589e11853dbddc1d99526e9c9bf170acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68576
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:52:17 +00:00
Elyes Haouas e8df32775d mb/lenovo/s230u/mainboard.c: Replace comma with semicolon
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I9e8ad533e939553a93e76f1dbb37fc98b53f06d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:51:56 +00:00
Elyes Haouas 000490a221 arm64/armv8: Use 'enum cb_err'
Change-Id: Ic4ce44865544c94c39e8582780a7eca7876f5c38
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-21 14:51:27 +00:00
Fred Reitberger d91f73b1d3 soc/amd/morgana/aoac: Remove to-do after review
Reviewed files and values match morgana ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6772b21110f74a77eef285da3e1f313ec6326cc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 14:50:15 +00:00
Fred Reitberger 0d98cc4844 soc/amd/morgana/i2c: Remove to-do after review
Reviewed files and values match morgana ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9d058b0f61b4784a1d83289e75705a6415405d0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 14:48:42 +00:00
Fred Reitberger 164b93bd9c soc/amd/morgana/include/soc/iomap.h: Remove to-do after review
Reviewed file and values match morgana ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I8f914432e0f55aa8050728e8cf41a3dee20990e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 14:47:48 +00:00
Jason Nien 29f1580086 mb/google/skyrim/port_descriptors: update DDI for MDN and Chausie
Add two new types for MDN DDI descriptor

BUG=b:228284940
TEST=Normal boot and S0i3 cycles

Signed-off-by: Jason Nien <finaljason@gmail.com>
Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-10-21 14:45:11 +00:00
Elyes Haouas 4c0299fbc8 nb/x4x/dq_dqs.c: Use 'enum cb_err'
Change-Id: I94dd6b1bb81bbc38ac5f89469b3ed7c83ca2a498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:35:26 +00:00
Elyes Haouas 6f9786bbcc nb/intel/x4x/raminit.c: Use 'enum cb_err'
Change-Id: I22d7e724e69b41c9fabdef785276dc428be2b400
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:32:40 +00:00
Matt DeVillier 6c8826de8f soc/intel/apollolake: Skip SMI lockdown on Apollolake
Commit d9ef02ce (soc/intel/apollolake: Lock down Global SMI) breaks
SMM/SMI on Apollolake (but not Geminilake), so guard it accordingly.

TEST=build/boot google/reef, verify SMM/SMI/SMMSTORE functional.

Change-Id: I00cbe046b61e6c342f7961670478d0ca8d365c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:31:21 +00:00
Martin Roth 95b5b025a0 util/lint: Fix linting outside of git repos
If the coreboot code is not in a git repository, the linters switch
from using `git ls-files` to find.  This requires some changes to
prevent the linters from looking at the wrong files which are
automatically excluded by git.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I81d138760c29a7c476280bb9d963f6be99c75d6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:30:42 +00:00
Elyes Haouas 60bdb327c6 nb/intel/i945/rcven.c: Use read32p()
Tested on unsupported mainboard (945g-m4).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1935308cc50abd651b52d6290d66180905c6a521
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-21 14:30:01 +00:00
Kevin Chiu 52163149b4 mb/google/brya: Create gladios ADL variant
Create the gladios variant of the brask reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:239513596
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_gladios

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I3dc99d97d8e30d9641f56616222dd68e3a0d548d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 23:56:10 +00:00
Fred Reitberger e1b3864f0e soc/amd/morgana/smi: Update smi definitions for morgana
Update the SMI definitions for morgana per PPR #57396, rev 1.52

Remove references to dropped SMITYPE_XHC2_PME in xhci.c to fix compile
errors.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6a9f05bcc6a6e4c94114ccbd07628629bdfabcba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20 21:40:15 +00:00
Martin Roth d282ae3889 Docs/releases: Finalize relnotes for the 4.18 release
The coreboot 4.18 release has been tagged, so the release notes can
now be finalized.

Updated with known issues.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I77676ddc42488e9635f1e6f995386490dca441c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68467
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-20 20:33:20 +00:00
Elyes Haouas 72c2e11beb nb/intel/i945/i945.h: Drop useless guard
i945.h file is not used to generate asl files.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 19:39:53 +00:00
Martin Roth 568670f94d arch/x86/include: Split CPUID access into separate file
To allow testing of code that uses CPUID calls, separate the actual
calls into a separate header file,  This allows the tests to emulate
the cpuid access without replacing the rest of the cpu.h definitions.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic5ee29f1fbb6304738f2eb7999cbcfdf8f7d4932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20 17:55:03 +00:00
Martin Roth 9c64c08b18 soc/amd/morgana: Add TODOs for common code to Kconfig
This allows us to see which of the common code blocks have been verified
and which have not.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Icb9eba5838013de75c408c28a4a7d3afacdf0674
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20 17:31:50 +00:00
Elyes Haouas 1a847a11be nb/intel/i945: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 17:29:48 +00:00
Elyes Haouas 4944609bd0 intel/i945: Use 'bool' for dual_channel and interleaved
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I055847c9b08795683fe2e1dfd7fcde49901fc973
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 17:29:15 +00:00
Matt DeVillier 411023af72 drivers/tpm: Move TPM init to end of device init phase
Boards which use an I2C TPM and do not use vboot will not have the
I2C bus initialized/ready at the start of the device init phase.
If TPM init is called before the bus, init will fail with I2C
transfer timeouts and a significantly lengthened boot time.

Resolves: https://ticket.coreboot.org/issues/429

TEST=build/boot google/reef w/o vboot, verify successful TPM init.

Change-Id: Ic47e465db1c06d8b79a1f0a06906843149b6dacd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68550
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20 17:22:57 +00:00
Martin Roth 3d242755ef mb/google/(guybrush|skyrim): Use a variable for APCB filename
We use the name of the APCB file repeatedly, so put it into a variable
so that it's easier to update.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I8684db2f7b2d68f0354e37bd8cdfc4f9cab44b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20 17:19:51 +00:00
Wonkyu Kim 6a342360da mb/google/rex: Skip sending the MBP HOB to save boot time
This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40 ms.

Boot time data
Before:
* 955:returning from FspSiliconInit 1,656,985 (274,416)
After:
* 955:returning from FspSiliconInit 1,593,036 (233,286)

BUG=b:252410202
TEST=Verified that boot time is reduced by ~40 msec.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I0d4f66940529b8d38d9658c769feba8b5c9b715e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68418
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-20 17:19:03 +00:00
Wonkyu Kim e5f6ff88c4 soc/intel/meteorlake: Add support to skip the MBP HOB
This patch adds the support to enable/disable skipping MBP HOB
from the devicetree based on mainboard requirement.
Porting the feature from commit 2bc54e7c00
("soc/intel/alderlake: Add support to skip the MBP HOB")

TEST=Build and boot to verify that the right value has been passed to
the FSP.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I360d33617b9d2626fce5600e861214b0747f57b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-20 17:18:45 +00:00
Felix Held 97e612586a soc/amd/*/uart: commonize UART code and MMIO device driver
Now that the SoC-specific UART controller data and the common code part
are cleanly separated, move the code to the common AMD UART support
block folder. The code is identical to the UART code in Cezanne,
Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts
related to the MMIO device driver.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:47:35 +00:00
Felix Held 8ebdbbc3cb soc/amd: move set_uart_config prototype to common UART header
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97860292fd3cd0330fec40edb31089cd6608906b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:47:11 +00:00
Felix Held ba35f3582e soc/amd: move all AOAC function prototypes to amdblocks/aoac.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3deae150cd1e20fff6507a0f0ba6a375fca430e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:46:31 +00:00
Felix Held 880364040a soc/amd/stoneyridge/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I813483bc0421043dc67c523f0ea2016a16a29f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:45:48 +00:00
Felix Held 957e232277 soc/amd/morgana/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I80278f1a098b389d78f8e9a9fb875c4e466dc5db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:45:17 +00:00
Felix Held ceab0fbc59 soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cfea274f4c9e908c11429199479aec037a00097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:45:08 +00:00
Felix Held 9fde88973a soc/amd/cezanne/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab1aec44c55570aa8085aeaf68ec69fe6de0f2ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:44:16 +00:00
Felix Held 6101dcf670 soc/amd/picasso/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I474e47059eaebcf0b9b77f66ee993f1963ebee77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:44:09 +00:00
Felix Held f1a03b1d6d soc/amd/stoneyridge: initialize GPIOs for serial console
Initialize the two GPIOs of the SoC UART if it's used for serial console
to be sure that the I/O mux is configured correctly without having to
rely on the bootblock_mainboard_early_init call to do this. This brings
Stoneyridge more in line with the other AMD SoCs. Since this code will
be factored out to the common AMD SoC code in a follow-up patch, the
function prototype is added to southbridge.h instead of creating a new
uart.h header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4aa6734e63dad204d22ce962b983cde6e3abd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:41:53 +00:00
Felix Held c6e4cc8873 soc/amd/*/uart: add missing soc/iomap.h include
soc/iomap.h provides the UART base address information used in the
uart_info struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7defd135dc888cfc7d6e1c106d72116425560576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:40:59 +00:00
Felix Held acd98d8772 soc/amd/stoneyridge/uart: add and use uart_info array
Introduce and use an array of soc_uart_ctrlr_info to align Stoneyridge
with the other AMD SoCs in order to allow commonization of the AMD SoC
UART code. Since the current Stoneyridge code doesn't provide or use
UART MMIO device operations, only the base addresses of the UART
controllers from this array are used for now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie868cd3e2f77b0f7253c9f6d91dd3bbc3e4b6b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:40:45 +00:00
Felix Held d2ebe16cb4 soc/amd: introduce and use common soc_uart_ctrlr_info struct
The SoC's uart_info structs all use the same anonymous uart_info struct
definition, so create a named struct for this in the common AMD SoC UART
header and use it in the SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:39:24 +00:00
Felix Held fb8c78b2ec soc/amd/morgana/uart: separate data and code
The goal of this is to be able to move most of the code over to the
common AMD blocks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib893720911114d61ee6b3fbbf1a2a3594500bcfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:38:57 +00:00
Felix Held f3976b67e0 soc/amd/mendocino/uart: separate data and code
The goal of this is to be able to move most of the code over to the
common AMD blocks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5077681b64dd68351340bd179838a174d8df1701
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:38:48 +00:00
Felix Held d85f25fbb9 soc/amd/cezanne/uart: separate data and code
The goal of this is to be able to move most of the code over to the
common AMD blocks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e585370a0de56787340788acfecc7931820566d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:38:19 +00:00
Felix Held 6c6c35f20c soc/amd/picasso/uart: separate data and code
The goal of this is to be able to move most of the code over to the
common AMD blocks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia496a4b29b25d4438ed8fc09bfe6f83e3fb768d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-10-20 16:38:13 +00:00
Shelley Chen 1b07797a7b soc/qualcomm/sc7280: Remove NVMe init
We are required to boot with eMMC enabled in the BIOS to store modem
calibration data.  Thus, it doesn't make sense to enable NVMe at boot
time since we will never boot from NVMe w/o eMMC.  We may as well take
the boot time reduction (~100ms) by eliminating NVMe initialization.

BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after disabling NVMe and make sure that it still boots
     Note that we are able to see a little over 100ms in boot time
     savings with this change.
     Before: 40:device configuration 824,021 (102,701)
     After:  40:device configuration 717,402 (44)

Cq-Depend: chromium:3964185
Change-Id: I94f614ba0369c073617949285c0781aef5c6263f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-20 16:34:01 +00:00
Shelley Chen d164feb726 mb/google/herobrine: Remove NVMe from device tree
We need to boot eMMC for modem calibration, there is not need for BIOS
to initialize NVMe anymore as the kernel will do so.  Removing the pci
device from the device tree as a first step.

BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after removing from the herobrine device tree.

Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-20 16:33:18 +00:00
Frank Wu 6d87ac57e2 mb/google/skyrim/var/frostflow: Update GPIO settings
Configure GPIOs based on GPIO_20221014.xlsx of frostflow.

BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I02272801c85a7c30d24c834a840e026225956fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20 16:25:22 +00:00
Frank Wu a6065ec328 mb/google/skyrim/var/frostflow: Generate RAM IDs for new memory parts
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H9JCNNNBK3MLYR-N6E             0 (0000)
MT62F1G32D4DR-031 WT:B         1 (0001)
H9JCNNNCP3MLYR-N6E             1 (0001)
MT62F2G32D8DR-031 WT:B         2 (0010)
H9JCNNNFA5MLYR-N6E             3 (0011)

BUG=b:250470704, b:247683159
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I34584092c938539c91d65501ebe34b00212b34d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20 16:24:41 +00:00
Frank Wu afd2f6ed62 spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6E
Add Hynix H9JCNNNFA5MLYR-N6E in the memory_parts.json and re-generate
the SPD.

BUG=b:250470704
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I9926a5859cf060e0bfa903f47d8a98c8d6115579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
2022-10-20 16:24:06 +00:00
Sumeet Pawnikar 4dba71fd25 Revert "drivers/intel/dptf: Add multiple fan support under dptf"
This reverts commit 672bd9bee5.

Reason for revert: Gmeet resolution dropped. When system starts
Gmeet video call, it uses the hardware accelerated encoder as per
the expectation. But, as soon as another system connects to the call,
the immediate fallback observed from hardware to software encoder.
Due to this, Gmeet resolution dropped from 720p to 180p.
Currently, this issue observed on AlderLake-N SoC based fanless
platforms. This issue is not seen on fan based systems.

BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alderlake-N systems. With this revert
Gmeet resolution drop not observed.

Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2022-10-20 14:54:09 +00:00