Commit Graph

3816 Commits

Author SHA1 Message Date
Stefan Reinauer e1025d0f7f Kontron 986LCD-M updates:
* ACPI updates: MCFG, HPET, FADT
* some mptable fixes for certain riser cards
* Use Channel XOR randomization
* Fix SuperIO HWM setup
* Enable all three network adapters

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:20:36 +00:00
Stefan Reinauer cc44b06d9d abuild:
- add configure only mode to easily and quickly check Config.lb and Option.lb
  files
- fix up cross compiler handling
- don't use in-place sed, not all sed versions can do it
- use perl instead of date to avoid non-gnu date trouble

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:00:50 +00:00
Stefan Reinauer a8e1168064 This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:

* fixed SMBus driver (was not compiled in before)
* fixed S-ATA/P-ATA combination
* Added warnings to drivers being called with a NULL dev->chip_info 
* Set subsystem ids for those boards that have none specified in Options.lb
* Fix license headers. The code was originally released under GPL v2 but
  some files sneaked in with a v2 or later header.
* some attempts to fix azalia/Intel HDA.. not working yet
* clean up and fix pci bridge handling code
* Add Config based GPI handling to LPC driver
* Add HPET enable function
* Enable clock gating where appropriate
* first attempt at USB debug console support (not working yet)
* Add required options to kontron board
* many other minor changes

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 14:54:18 +00:00
Stefan Reinauer 6df0c62b68 Add support for the LPC47M182 to superiotool
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 14:48:20 +00:00
Myles Watson 34b1d4ef37 This patch adds ACPI support for Tyan s2891, s2892, and s2895. There is still
a problem with IRQ 9, but besides that Linux is happy.  BSOD in Windows still.

changes by file:

src/mainboard/tyan/s289X/Options.lb:
	Add options and defaults for ACPI tables and resources.

src/mainboard/tyan/s289X/mainboard.c:
	Add high_tables resource ala Stefan's code for the Kontron.

src/mainboard/tyan/s289X/acpi_tables.c:
	Fill out the ACPI tables, using existing code where possible.
	Only the madt is different between the boards, to be combined later.

src/mainboard/tyan/s289X/Config.lb:
	Compile in acpi_tables.c and dsdt.dsl.
	Turn on the parallel port and the real-time-clock.

src/mainboard/tyan/s289x/dsdt.dsl:
	The board layout (thanks Rudolf) and interrupts from mptable.c

src/mainboard/tyan/s289x/mptable.c:
	Minor formatting changes to make them diff better.

src/superio/smsc/lpc47b397/superio.c:
	Correct the size of the real-time-clock so it can be where it belongs.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 20:56:54 +00:00
Myles Watson 283a494521 This patch adds common elements for ck804-based boards.
changes by file:
src/northbridge/amd/amdk8/northbridge.c:
	Add high tables code ala Stefan's code for the i945.

src/southbridge/nvidia/ck804/ck804_lpc.c:
	Enable High Precision Event Timers.
	Add pm_base for ACPI.

src/southbridge/nvidia/ck804/ck804_fadt.c:
	Since fadt is only dependent on the Southbridge, add it here.

src/southbridge/nvidia/ck804/Config.lb:
	Compile in ck804_fadt.c

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 20:39:27 +00:00
Myles Watson 210b83e764 This patch adds empty acpi_fill_slit functions so they build again.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 18:44:34 +00:00
Myles Watson 0b4c9f08c7 This patch makes the boards use a single amdk8_util.asl. There are only
whitespace differences between this file and the amdk8_util.asl from
asus/m2v_mxe.

It also enables SLIT filling if you have one, zeroes the unused fields in the
srat_lapic structure, and adds some declarations in acpi.h.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 18:06:47 +00:00
Marc Jones 8f210766d5 Add some basic K8 MSRs.
Fix bash script type.
Removed const return type on msraddrbyname() to fix gcc warning/error.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-08 04:37:39 +00:00
Carl-Daniel Hailfinger 3b1a955cce FreeBSD definitions of (read|write)[bwl] collide with our own. Before we
attempt trickery, we can simply rename the accessor functions.

Patch created with the help of Coccinelle.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 22:26:00 +00:00
Stefan Reinauer 45cc550c3a Some updates for core/core duo/core2/core2 duo cpus.
The microcode is from Intel's Linux microcode file, so it's unproblematic.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:54:15 +00:00
Stefan Reinauer 3b387458b5 * fix a minor power state issue in the ich7 smm handler
* move mainboard dependent code into a mainboard SMI handler.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:52:36 +00:00
Stefan Reinauer 43b29cf891 Fix mmconf (PCIe memory mapped config space access) support in v2. It was
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.

Create wrapper functions similar to the io pci config space ones.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:11:52 +00:00
Stefan Reinauer ae762b5d3b use include file for i8259 where appropriate (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 18:39:54 +00:00
Stefan Reinauer 1894463787 clean up qemu target config (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 18:38:28 +00:00
Stefan Reinauer 0d348f919c fix strstr. Seems the function never worked before, except the searched
substring is at the end.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:43:20 +00:00
Stefan Reinauer 8dcd50b155 fix a bunch of cast and type warnings and don't call the apic "nvram", that
doesn't make no sense. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:24:29 +00:00
Stefan Reinauer 054c7235c3 use pointers instead of size_t when dealing with pointers. Also fix a few
warnings (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:22:35 +00:00
Stefan Reinauer f8c77e82c5 use inb instead of outb for delays in usb debug code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:21:23 +00:00
Stefan Reinauer 9cbbc7902a really clean out all compile time generated files (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:20:17 +00:00
Carl-Daniel Hailfinger 59c36f97db During the conversion of flash chip accesses to helper functions, I
spotted assignments to volatile variables which were neither placed
inside the mmapped ROM area nor were they counters.
Due to the use of accessor functions, volatile usage can be reduced
significantly because the accessor functions take care of actually
performing the reads/writes correctly.

The following semantic patch spotted them (linebreak in python string
for readability reasons, please remove before usage):
@r exists@
expression b;
typedef uint8_t;
volatile uint8_t a;
position p1;
@@
 a@p1 = readb(b);

@script:python@
p1 << r.p1;
a << r.a;
b << r.b;
@@
print "* file: %s line %s has assignment to unnecessarily volatile
variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b)

Result was:
HANDLING: sst28sf040.c
* file: sst28sf040.c line 44 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 43 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 42 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 41 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 40 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 39 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 38 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 58 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 57 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 56 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 55 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 54 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 53 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 52 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);

The following semantic patch uses the spatch builtin match printing
functionality by prepending a "*" to the line with the pattern:
@@
expression b;
typedef uint8_t;
volatile uint8_t a;
@@
* a = readb(b);

Result is:
HANDLING: sst28sf040.c
diff =
--- sst28sf040.c        2009-03-06 01:04:49.000000000 +0100
@@ -35,13 +35,6 @@ static __inline__ void protect_28sf040(v
        /* ask compiler not to optimize this */
        volatile uint8_t tmp;
 
-       tmp = readb(bios + 0x1823);
-       tmp = readb(bios + 0x1820);
-       tmp = readb(bios + 0x1822);
-       tmp = readb(bios + 0x0418);
-       tmp = readb(bios + 0x041B);
-       tmp = readb(bios + 0x0419);
-       tmp = readb(bios + 0x040A);
 }
 
 static __inline__ void unprotect_28sf040(volatile uint8_t *bios)
@@ -49,13 +42,6 @@ static __inline__ void unprotect_28sf040
        /* ask compiler not to optimize this */
        volatile uint8_t tmp;
 
-       tmp = readb(bios + 0x1823);
-       tmp = readb(bios + 0x1820);
-       tmp = readb(bios + 0x1822);
-       tmp = readb(bios + 0x0418);
-       tmp = readb(bios + 0x041B);
-       tmp = readb(bios + 0x0419);
-       tmp = readb(bios + 0x041A);
 }
 
 static __inline__ int erase_sector_28sf040(volatile uint8_t *bios,

It's arguably a bit easier to read if you get used to the leading "-"
for matching lines.

This patch was enabled by Coccinelle:
http://www.emn.fr/x-info/coccinelle/


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@settoplinux.org>
-- 
http://www.hailfinger.org/


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 00:40:25 +00:00
Carl-Daniel Hailfinger bba113ec07 If get_pbus() is called for a device which has no parent/ancestor bus
with nonzero PCI bus operations, get_pbus() will get stuck in a silent
endless loop.
Detect the endless loop and break out with an error message.

Such a situation can happen if the device tree is not yet
initialized/walked completely.

This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was
used in early mainboard code for the AMD DBM690T. Instead, the code will
now die() with a meaningful error message.

Thanks to Ward Vandewege for testing my patches to track down that bug.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-05 19:33:12 +00:00
Carl-Daniel Hailfinger ac12ecd27a flashrom: Use helper functions to access flash chips.
Right now we perform direct pointer manipulation without any abstraction
to read from and write to memory mapped flash chips. That makes it
impossible to drive any flasher which does not mmap the whole chip.

Using helper functions readb() and writeb() allows a driver for external
flash programmers like Paraflasher to replace readb and writeb with
calls to its own chip access routines.

This patch has the additional advantage of removing lots of unnecessary
casts to volatile uint8_t * and now-superfluous parentheses which caused
poor readability.

I used the semantic patcher Coccinelle to create this patch. The
semantic patch follows:
@@
expression a;
typedef uint8_t;
volatile uint8_t *b;
@@
- *(b) = (a);
+ writeb(a, b);
@@
volatile uint8_t *b;
@@
- *(b)
+ readb(b)
@@
type T;
T b;
@@
(
 readb
|
 writeb
)
 (...,
- (T)
- (b)
+ b
 )

In contrast to a sed script, the semantic patch performs type checking
before converting anything.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
Tested-by: Joe Julian


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-05 19:24:22 +00:00
Carl-Daniel Hailfinger 51001fbd81 I just went on a bugfix frenzy and fixed all printk format warnings
triggered by the AMD 690/SB600 targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04 01:06:41 +00:00
Stefan Reinauer 4b95ced365 fix make clean as suggested by Myles Watson.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04 00:25:44 +00:00
Rudolf Marek 6b2e760f03 Small bug somehow slipped there. The method body length is incorrectly computed.
The attached patch fixes this. I did not spotted that because the return arg is
moved just outside of method and I have overseen the closing }
 
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-02 22:45:31 +00:00
Rudolf Marek fc19248501 (Trivial) Add missing header file.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01 18:05:25 +00:00
Stefan Reinauer 36c83404a3 Some changes required to get yabel working on v2 (and they generally make
sense, too). Have one u64 instead of three.

In order to use the old bios emulator, you have to do nothing. (Default, if
CONFIG_PCI_ROM_RUN is enabled)

In order to use yabel in your target, you need to add the following lines to
your config:
  uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
  default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1

In order to use vm86 in your target, you need to add the following lines to
your config:
  uses CONFIG_PCI_OPTION_ROM_RUN_VM86
  default CONFIG_PCI_OPTION_ROM_RUN_VM86=1
Note: vm86 only works on platforms with _RAMBASE in the lower megabyte.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01 10:16:01 +00:00
Stefan Reinauer 2b34db8d1d coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 20:10:20 +00:00
Stefan Reinauer 3c924d2f48 fix those two boards that broke due to the config tool fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 17:19:55 +00:00
Stefan Reinauer 9987ad806f This is a small fix for the last checkin (does not fix those two boards) that
caused same filenames to still cause objects being dropped from the build list
- which was the whole purpose of the patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 17:09:29 +00:00
Stefan Reinauer 21c8b5ab5c With this patch the v2 build system will create a directory hierarchy
similar to what v3 does. This is required to have two source files with
the same name but in different directories. (As in, two different SuperIOs on
board, with a superio.c each)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 12:50:32 +00:00
Stefan Reinauer 3c7f46b422 Generic approach of putting BIOS tables at the end of memory
(in addition to their low locations)

This adds the kontron 986LCD-M and the i945 as a sample.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-27 23:09:55 +00:00
Myles Watson 678d6140a5 This patch makes several CMOS/NVRAM reads dependent on whether there's a table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-27 17:51:16 +00:00
Zheng Bao a85c0059f3 flashrom: Add SST25VF040.REMS with TEST_OK_ PROBE READ
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-25 08:07:33 +00:00
Mart Raudsepp c5a2ec6f96 libpayload: Fix build when both USB and PS/2 keyboard support is disabled
libpayload uses -Werror for some reason right now, and the
variable 'c' in curses_getchar is only used if CONFIG_USB_HID
or CONFIG_PC_KEYBOARD is defined, giving an unused variable
warning that gets promoted to an error.
So wrap the variable declaration around appropriate #ifdef's

Signed-off-by: Mart Raudsepp <leio@gentoo.org>
Acked-by: Ulf Jordan <jordan@chalmers.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-22 23:13:33 +00:00
Peter Stuge bc8744e1bf flashrom: SST29EE020A TEST_OK_ PROBE READ ERASE WRITE
Report by Holger Mickler. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-22 21:07:28 +00:00
Rudolf Marek fe849b2ff7 This patch is for AMD boards which can do the P state generation. This just
removes the ugly binary DSDT patching and all other related stuff. Stick to
infrastructure in previous patch.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-19 08:39:16 +00:00
Carl-Daniel Hailfinger 7ad11e8d33 Carl-Daniel's part:
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and 
mainboard_$VENDOR_$BOARD_config to mainboard_config.

Ron's part:
The config change that makes the naming change not break every build.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-18 20:41:57 +00:00
Carl-Daniel Hailfinger d58671c4bf Add QWord support to acpigen.
Add TOM2 to the K8 DSDT.

Thanks to Rudolf Marek for testing and fixing this patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-17 21:38:51 +00:00
Ulf Jordan 142cad1503 Bayou: Clean up Bayou's window after returning from a payload.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-17 16:23:26 +00:00
Patrick Georgi 08afc6d9e0 Unify CAR so the same compiled code does the right thing on both
K8 and Fam10+ CPUs.

What this patch does:
1. Enable SSE (to get some more registers to play with)
2. Determine CPUID, and stash it in an XMM register, and reference
   value for comparison in another XMM register (mangled somewhat to
   simplify inequality comparisons)
3. Add a macro jmp_if_k8, which jumps if the CPU is K8
   (using an SSE compare)
4. Replace #if CAR_FAM10 sections with runtime checks using jmp_if_k8.
   This is pretty mechanical work. The macro uses local labels
   (1: and 2:) to prevent namespace issues
5. At one time, CPU_ADDR_BITS is used to fill a register. This is
   replaced with hardcoded values for both cases, and switched
   appropriately.
6. Disable SSE

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-17 12:56:58 +00:00
Ronald G. Minnich b575d67b9a This is a safety measure, since the shipping buildrom fails badly at present.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-15 23:32:57 +00:00
Stefan Reinauer 5389c7f72b - Fix up amd pistachio and dbm690t.
- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs
  on some platforms.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-15 02:53:18 +00:00
Rudolf Marek a175533dc3 Change Log:
Bellongs to r3947

Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14 16:23:16 +00:00
Rudolf Marek 537bd5f637 Bellongs to r3946
Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14 15:42:42 +00:00
Rudolf Marek f997b5554a Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14 15:40:23 +00:00
Ronald G. Minnich 66948f7e8c This target is dead.
The company is dead. 

It causes builds to fail, and that is not a problem we need to have. 

Removing it to remove the problems it causes. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-13 20:20:21 +00:00
Carl-Daniel Hailfinger 31197a61d9 Increase ROM_IMAGE_SIZE for the agami aruma to resolve overlapping
sections.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-13 18:46:22 +00:00
Myles Watson 552b327ca3 This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 21:30:06 +00:00