smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE
and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the
same MSR that has been locked by another thread.
Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock
bit.
Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
While the fall through comment is sufficient for gcc to notice that the
fall-through is intentional, clang requires a special attribute which
also works for gcc. Update the documentation to use this attribute
instead of the comment.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I08dbac8ff1f9e04770a03fb74fabf0d397b50989
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71102
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch adds files required for ramstage and SMM.
1. Add file required for ramstage (mainboard.c)
2. Add smihandler.c for SMM
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch will initialize EC for mtlrvp which includes,
1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC)
2. Add respective ACPI configuration
3. Add ec.c required for ramstage
4. Program EC ranges as part of devicetree.cb
5. Enable VBOOT in Kconfig
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with
CHROME_EC using subsequent patches in the train
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As _Static_assert() is a compiler built-in, <assert.h> is not needed.
Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Updating from commit id 2047412:
2022-11-29 17:52:03 +0800 - (Elkhart Lake MR5 FSP)
to commit id 6f2f17f:
2022-12-14 12:36:46 -0700 - (Deleted old Release Notes and Integration Guides)
This brings in 6 new commits:
6f2f17f Deleted old Release Notes and Integration Guides
3868f73 Updated for SGXFlex - New UPDs available
a649f0f Whitley FSP 2.2.0.3A
f99be62 Merge branch 'master' of https://github.com/intel/FSP
1787bc7 Updated IoT ADL-PS MR1 (3404_00) FSP
1e833b0 Elkhart Lake MR5 FSP
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1dbd85ef06b057305428d42dd6cd6de0f2618439
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Updating from commit id e8efa5d:
2022-05-30 15:47:07 +0530 - (sc7180/boot: Update qclib blobs binaries from 44 to 46)
to commit id 33cc4f2:
2022-10-26 14:21:20 +0530 - (sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69)
This brings in 10 new commits:
33cc4f2 sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69
6c82214 sc7180/boot: Update qclib blobs binaries from 48 to 50
e570e02 Reland "sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063"
6206ab8 Revert "sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063"
82bbf78 sc7280/aop: Update aop blobs binaries and release notes version from 379 to 410
e3a760d sc7180/boot: Update qclib blobs binaries from 46 to 48
741abaa sc7280/boot/shrm: Update qclib blobs binaries from 30 to 35
436cb87 sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063
3f44ba0 sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes update from 044 to 050
eef51c6 sc7280/qcsec: Update qcsec blobs binaries and release notes for 27
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I72b91e384b74e4e44864ef5f29be78ebac4262fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch fixes a hidden issue present inside FSP-S while coreboot
decides to skip performing MP initialization by overriding FSP-S UPDs
as below:
1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need
to use coreboot wrapper for performing any
operation over APs.
2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided
to skip FSP running CPU feature programming.
Unfortunately, the assumption of coreboot is not aligned with FSP when
it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of
the APs (Application Processors) upon passing `NULL` pointer to the
`CpuMpPpi` FSP-S UPD.
FSP-S creates its own infrastructure code after seeing the CpuMpPpi
UPD is set to `NULL`. FSP requires the CpuMpPei module, file name
`UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker`
to perform those additional initialization which is not relevant for
the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid
running CPU feature programming on APs).
Additionally, FSP-S binary size has increased by ~30KB (irrespective of
being compressed) with the inclusion of the CpuMpPei module, which is
eventually not meaningful for coreboot.
Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config
unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD
and avoid APs getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.
Ideally, FSP should have avoided all AP related operations when
coreboot requested FSP to skip MP init by overriding required UPDs.
TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on
Google/Redrix, Kano, Taeko devices with SkipMpInit=1.
Without this patch:
Here is the CPU AP logs coming from the EDK2 (open-source)
[UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the
CpuMpPpi UPD.
[SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6
[SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2
CpuMpPei.efi PROGRESS CODE: V03020002 I0
[SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
[SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE,
Peim notify entry point: 76FA0239
AP Loop Mode is 2
GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found.
CPU[0000]: Microcode revision = 00000000, expected = 00000000
[SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6
Does not find any stored CPU BIST information from PPI!
APICID - 0x00000000, BIST - 0x00000000
[SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97
[SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA
[SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A
PROGRESS CODE: V03020003 I0
With this patch:
No instance of `CpuMpPei` has been found in the AP UART log with FSP
debug enabled.
This patch is backported from
commit 8409f156d5 (soc/intel/alderlake:
Remove dependency of FSP-S CpuMpPei Module)
Change-Id: I7d9fb37ca1cd4bf325edc951ee7293e459fa2ea4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70600
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
The details about how the CPU multiprocessor init (MP) has migrated
from coreboot to FSP can be found in
https://doc.coreboot.org/soc/intel/mp_init/mp_init.html.
The major reason behind this migration is to support the Intel
proprietary and restricted CPU feature programming which can't be
performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part
of coreboot MP Init flow (prior to calling FSP-S). Hence, the new
flow introduced with Tiger Lake platform forced having monolithic
MP Init peformed by FSP (using coreboot MP PPI wrapper code).
The last 3-4 years of FSP doing MP Init has demonstrated ample
issues during platform bringup which is specific to UEFI MP Service
implementation and not relevant to open source coreboot. This new
flow makes the debug and validation aspect complicated where
any FSP MP Init code changes should have been validated with coreboot
MP PPI wrapper else might cause some failure, unfortunately,
the validation commitment has never been met, hence, issue debugging
is the only solution that remains in practice.
Most importantly, the restricted feature programming which demanded
closed source MP Init (for features like SGX and C6DRAM) has never
been enabled in coreboot (starting with Alder Lake, the SGX feature
has been dropped).
This patch attempts to decouple FSP-S doing MP Init from the rest
of the FSP-S silicon init and introduces 2nd MultiPhase SI init
which allows bootloader to perform the mandatory SoC programming
before FSP-S has done with PM programming (a.k.a set the reset CPL).
The core/uncore BWG suggests the minimum SoC programming before
BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2
to perform the required CPU programming before enabling the BIOS
Reset CPL.
This implementation would allow us to get rid of FSP running CPU
feature programming and additionally make several EDK2 MP service
modules optional (those are packed to create FSP-S blob).
In summary, this change would allow coreboot to utilize open source
MP init without running into FSP-S related code blocks.
Note: At present, Intel Meteor Lake FSP doesn't have support for
MultiPhase SI Init, Index 2 (submitted a FSP code changes over
chrome-internal to enable this feature to decouple MP Init from
FSP-S init).
This patch is backported from
commit b6c3a0325b (soc/intel/alderlake:
Implement MultiPhase SI Init Index 2 callback).
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Perform several thousands cycles of suspend test and power cycle
without running into any issue.
Change-Id: I2ea1a8bb2b142e39c2bc9d248b7fd0041366c0db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70558
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch implements mps2_noop_get_number_of_processors() API with
minimal information required for Intel MTL FSP to utilise the
`MP_SERVICES_PPI_V2_NOOP` config.
The major difference between Intel ADL and MTL FSP in terms of doing
CPU feature programming aka utilizing MP PPI wrapper code is that,
starting with MTL, FSP has dropped the `SkipMpInit` UPD.
It means now, coreboot doesn't have any way to skip FSP doing MP Init
operation. But during ADL, coreboot had introduced the
MP_SERVICES_PPI_V2_NOOP config that is used to skip FSP about
actually running any CPU feature programming on APs.
The idea is to use the same config even in MTL to provide only the
must have information (to bypass any assert in FSP during debug image)
to FSP.
Passing `FSP_UNSUPPORTED` from mps2_noop_get_number_of_processors()
results in `assert` while compiling FSP in debug mode hence,
implementing the function to pass only the information about BSP being
the active processor along with passing `FSP_SUCCESS` (eventually it
makes FSP happy and doesn't run into any issue in debug and/or release
mode).
TEST=Able to build and boot Google/Rex and Google/Kano while
coreboot skip calling into FSP for doing MP init.
Change-Id: I75d7e151699782210e86be564b0055d572cacc3f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70555
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add EC memory layout and Q events for AMD Cezanne based boards,
the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE
5570E.
Change-Id: I87806b830b3d58a6ce3b89f45b5a07f4502a87f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68333
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove flag in VBTs for 'Use fixed resolution at boot' to allow FSP/GOP
display init to use native panel resolution instead.
TEST=build/boot multiple google/octopus variants with edk2 payload,
verify boot logo not distorted/stretched.
Change-Id: Ia31ff28379282619dfa22a955bee1a768bb54bb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Boot menus are too small at native 4K res on some panels, so
set fixed display resolution to 1920x1090p
TEST=build/boot KOHAKU with 4K display, verify boot menu text legible.
Change-Id: I82563c83de7ab302151f60d86b8a6824330d03ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot has been keeping a mirror of all the toolchain packages used
for releases for quite a while now. This adds an option to fetch the
packages from the coreboot mirror directly to buildgcc.
This can help with both our releases and when one of the various
servers experiences interruptions or changes a path.
To do this, the URL and filename needed to be split apart, which led to
quite a few changes in the buildgcc script.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
It's hidden behind the configuration option `CONFIG_ROMSTAGE_LIBHWBASE'.
This also adds some glue code to use the coreboot console for debug
output and our monotonic timer framework as timer backend.
Running Ada code in romstage and more particular libhwbase brings a few
challenges as global initialized variables are not supported in
Cache-As-Ram mode.
1. The libhwbase dynamic mmio driver implementation makes the Gnat
compiler generate some global initialized variables.
For this reason, when compiled for romstage or for romstage and
ramstage the static mmio driver is enforced (`HWBASE_STATIC_MMIO').
2. The Gnat compiler generates elaboration functions to initialize
program data at runtime. These elaboration functions are called by
the romstage_adainit() function.
The data references symbols suffixed by `_E'. Even though these
symbols, at compilation time, do not contain any data and are
filled with zeros, the Gnat compiler installs them in the .data
section.
Since these symbols are actually filled with zeros, it is safe to
install them in the .bss section.
cf. https://docs.adacore.com/gnat_ugn-docs/html/gnat_ugn/gnat_ugn/elaboration_order_handling_in_gnat.html#elaboration-code
This patch requires the libhwbase
https://review.coreboot.org/c/libhwbase/+/69854 CL.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=libhwbae compiles for romstage and loads successfully
Change-Id: I670249d33506e886a683e55d1589cb2bf9b16aa3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70275
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If selected, libgnat is linked into romstage. In addition, a call to
romstage_adainit() is added to support Ada program data
initialization.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Ada code compiles for romstage and loads successfully
Change-Id: I74f0460f6b14fde2b4bd6391e1782b2e5b217707
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70274
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hexdump command is not available in coreboot-sdk. Replace it with
equivalent implementation using commands that are present in the
container.
TEST=Passed "VP46XX" as prefix variable and it produced the same
crc32 result before and after the change.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Icad93933335b8c5ebd8fee74cc9aaed36bb56482
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
According to Intel doc#630774, BIOS should clear Host Interrupt Status
if it has read all the slots of the message from the ME circular buffer.
Since this is not found in client ME document, add a Kconfig
SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server
ME SKU.
On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the
change can avoid seeing below Linux warning during boot with Linux
v5.12:
[ 17.868929] irq 16: nobody cared (try booting with the "irqpoll" option)
[ 17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0
[ 17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1
[ 17.922327] Call Trace:
[ 17.927780] <IRQ>
[ 17.932253] dump_stack+0x64/0x7c
[ 17.939640] __report_bad_irq+0x37/0xb1
[ 17.948206] note_interrupt.cold.11+0xa/0x63
[ 17.957713] handle_irq_event_percpu+0x6a/0x80
[ 17.967626] handle_irq_event+0x2a/0x50
[ 17.976163] handle_fasteoi_irq+0x9e/0x140
[ 17.985305] __common_interrupt+0x38/0x90
[ 17.994255] common_interrupt+0x7a/0xa0
[ 18.002821] </IRQ>
[ 18.007514] asm_common_interrupt+0x1e/0x40
Change-Id: I1cf21112870e53a11134d43e461b735ead239717
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
In some cases, fw_config is used for ids like sar_id, sku_id etc.
To avoid calling fw_config_probe over and over, hence provide the
method to return the value then caller can use the switch case
instead of if else statement.
TEST=get fw_config field value on nivviks.
[INFO ] fw_config get field name=DB_USB, mask=0x3, shift=0, value =0x1
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iae89668e8fe7322d5a4dcbf88a97d7ed36619af5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
With commit 34a7e66faa ("util/cbfstool: Add a new mechanism to
provide a memory map"), builds are failing on 32-bit platforms with:
../cbfstool/cbfstool.c:397:30: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat]
printf("Image SIZE %lu\n", image_size);
~~~ ^~~~~~~~~~
%zu
Change the format specifier from %lu to %zu.
TEST=`emerge-cherry coreboot-utils` now succeeds
Change-Id: I3602f57cf91c330122019bfa921faef6deb2b4ce
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70848
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Based upon hardware differences from mc_ehl2, disable RP7
and enable RP3 and RP5.
Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new mc_ehl variant, which is based on mc_ehl2 implementation.
This patch uses a copy of mc_ehl2 with changes only in naming
as a starting point for the new mc_ehl3 variant.
Follow-up patches will introduce the functional changes against
mc_ehl3.
Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
With commit 0110e1abe0 ("util/genbuild_h: Update printf %d to %s for
sh compatability"), the ChromeOS coreboot build is failing with:
In file included from src/lib/version.c:4:
/build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5473/work/build/nivviks/build.h:10:32: error: 'v1' undeclared here (not in a function)
10 | #define COREBOOT_MAJOR_VERSION v1
| ^~
src/lib/version.c:35:46: note: in expansion of macro 'COREBOOT_MAJOR_VERSION'
35 | const unsigned int coreboot_major_revision = COREBOOT_MAJOR_VERSION;
| ^~~~~~~~~~~~~~~~~~~~~~
/build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5473/work/build/nivviks/build.h:11:32: error: 'v9308' undeclared here (not in a function)
11 | #define COREBOOT_MINOR_VERSION v9308
| ^~~~~
src/lib/version.c:36:46: note: in expansion of macro 'COREBOOT_MINOR_VERSION'
36 | const unsigned int coreboot_minor_revision = COREBOOT_MINOR_VERSION;
| ^~~~~~~~~~~~~~~~~~~~~~
This is because the ChromeOS coreboot repo has a tag which is not in the
expected <major>.<minor> format:
$ git tag
v1.9308_26_0.0.22
Change genbuild_h.sh to only use the version from `git describe` if it's
in the expected <major>.<minor> format.
TEST=ChromeOS coreboot build now succeeds, with versions set to 0:
#define COREBOOT_MAJOR_VERSION 0
#define COREBOOT_MINOR_VERSION 0
Building upstream coreboot, the versions are still set correctly:
#define COREBOOT_MAJOR_VERSION 4
#define COREBOOT_MINOR_VERSION 18
Change-Id: I81b2317a83cdec4cc2aad60af2990e5e3f4ad694
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Usha P <usha.p@intel.com>
On nissa, sending EOP late improves boot time by about 57ms.
Before (SOC_INTEL_CSE_SEND_EOP_EARLY):
943:after sending EOP to ME 931,206 (58,431)
943:after sending EOP to ME 932,911 (58,427)
943:after sending EOP to ME 930,908 (58,429)
943:after sending EOP to ME 941,357 (61,748)
943:after sending EOP to ME 933,289 (62,050)
943:after sending EOP to ME 939,578 (62,453)
943:after sending EOP to ME 932,491 (62,050)
943:after sending EOP to ME 929,693 (62,655)
943:after sending EOP to ME 942,247 (62,654)
943:after sending EOP to ME 936,984 (61,751)
After (SOC_INTEL_CSE_SEND_EOP_LATE):
943:after sending EOP to ME 1,107,816 (3,498)
943:after sending EOP to ME 1,053,286 (25,212)
943:after sending EOP to ME 1,124,095 (3,511)
943:after sending EOP to ME 1,098,591 (3,498)
943:after sending EOP to ME 1,107,772 (3,499)
943:after sending EOP to ME 1,080,008 (45,969)
943:after sending EOP to ME 1,081,754 (8,024)
943:after sending EOP to ME 1,109,193 (4,102)
943:after sending EOP to ME 1,088,866 (4,201)
943:after sending EOP to ME 1,081,684 (4,203)
BUG=b:247902068
TEST=EOP time is improved on nissa (measurements above).
Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Utilities like kconfig/conf now will be built inside tests build tree.
It will eliminate possible colisions of target names when using test
framework in more than one place (see CB:70110)
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4c1eb901c921f4ec6ee8985b154362153c5fd0e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70359
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Utility will be built while executing kconfig targets so it is not
necessary to keep hard dependency on kconfig here.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I578f3e1d9de63e91ded44746539265bcd55bf579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70298
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some tools based on test framework might require defconfig other
than one set in tests framework.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If53b9a54ef7389dd979dfe772e6946439f7d6a62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70109
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows for linking selected files with system libc. This
allows for creating libraries interacting with filesystem, standard I/O
and other parts of system. Until now it was only possible using CMocka
proxy functions or functions not masked by code under test.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I652362ba61a25e974d706357fc36479ccee763e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
This patch is to change method of HID assignment with compatible id
style in nau8315_config and allow mainboards to set it.
Signed-off-by: David Lin <CTLIN0@nuvoton.com>
Change-Id: Ia6f02e495eeb06290947edc9e44fa25a4ce18956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69965
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Enable wifi sar function for yaviks.
Use the fw_config to separate SAR setting for different wifi card.
BUG=259199095
TEST=build, enabled iwlwifi debug, and check dmesg
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Update SX9324 RegProxCtrl0 register settings based on tunning value
from P-sensor vendor.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28 on Pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: If471a6fee5a3daeac1958709415b2d5e1329b81b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Remove the `const` property from chip_get_common_soc_structure so that
the returned values can be overwritten as required.
Cc: th3fanbus@gmail.com
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7d3db0bc119cd9b9b276abd68754e750e06a788c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Increase the default linear framebuffer max height/width for desktops
so that native display resolution works properly on 2160p and 1440p
ultrawide displays.
TEST=build/boot google/fizz, verify libgfxinit display init works
properly on 3440x1440p and 3840x2160p displays.
Change-Id: I95a1f1275a4faea195b73997c648023119807958
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Unlike gcc, a clang build will fail when only a comment is used to
indicate that the fallthough is intended. To fix the clang build, use
__fallthrough instead. This will fix the build errors introduced by
commit f45c7671d9 ("Set x86_64 as supported architecture for clang")
that enabled clang builds for a case that uses yabel to run the VBIOS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ed337025adeb833f352d198fc0f13b5e1c209c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70889
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The original value of the `DevIntConfigPtr` is unknown, and there's no
way to be absolutely certain that it actually points to usable memory.
Instead of copying the data, update the pointer's address to reference
the global variable directly. It is assumed that FSP does not write to
the memory pointed by `DevIntConfigPtr`. Confirming this assumption is
pointless; one might as well reimplement FSP instead.
Change-Id: I90594cc09e3fa2aef98658441c323a44a869635b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65217
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This will help to integrate RO SPL table in RO partitions such that it
is used before PSP verstage is loaded. After PSP verstage, SPL table in
RW partition gets used.
BUG=b:243470283
TEST=Build Skyrim BIOS image and boot to OS.
Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Johnny Lin