Commit Graph

46620 Commits

Author SHA1 Message Date
Jes Klinke 19baa9d51e i2c: Add configurable I2C transfer timeout
This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US,
which controls how long to wait for an I2C devices to
produce/accept all the data bytes in a single transfer.
(The device can delay transfer by stretching the clock of
the ack bit.)

The default value of this new setting is 500ms.  Existing
code had timeouts anywhere from tens of milliseconds to a
full second beween various drivers.  Drivers can still have
their own shorter timeouts for setup/communication with the
I2C host controller (as opposed to transactions with I2C
devices on the bus.)

In general, the timeout is not meant to be reached except in
situations where there is already serious problem with the
boot, and serves to make sure that some useful diagnostic
output is produced on the console.

Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-15 22:06:27 +00:00
Subrata Banik ca82e6161a util/ifdtool: Add Meteor Lake platform support under IFDv2
BUG=b:224325352
TEST=Able to build ifdtool.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3564efa27d0271286435284e745458aada987008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-15 19:22:49 +00:00
Michael Niewöhner d3b85223fd soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.

Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15 19:22:19 +00:00
Sean Rhodes bba7e601a8 intel/common/block: Add APL and GLK PCI IDs for HDA
Add PCI ID's for APL/GLK so they can use HDA.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-15 19:21:46 +00:00
Kevin Chiu 29919f81fa mb/google/guybrush/var/nipperkin: update APU STT setting
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     update the thermal setting value by measurement and
     pass the thermal performance test

Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-15 19:19:36 +00:00
Frank Wu bd0ba39172 mb/google/brya/var/banshee: Add camera privacy setting
Using the GPP_F19 as privacy switch for camera in banshee.

BUG=b:223712143, b:216110896
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-15 19:19:21 +00:00
Werner Zeh 9b565de3a0 lib/spd: Do not print part number if it is not available
If the DRAM part number is not available in the SPD data (meaning filled
with 0x00) do not print it in the log.

Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15 19:18:54 +00:00
Rex-BC Chen 69e3cab7f9 soc/mediatek/mt8186: change pmic hwcid from warning to info
The pmic hwcid dumping should not be a warning, so we modify it to info.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15 19:17:48 +00:00
Rex-BC Chen 129b8ae551 soc/mediatek/common: Add halt() after triggering wdt reset
It's more reasonable to halt when we trigger watchdog reset because
the whole system should be reset afterwards.

BUG=b:222217317
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15 19:17:12 +00:00
MAULIK V VAGHELA a4cdb5b381 mb/google/brya: Disable C1-state auto demotion for Brya & Brask
C1-state auto demotion feature allows hardware to determine C1-state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.

Also, disabling this feature results in 110 mW power savings during
video playback.

Note that C1state Autodemotion feature is not applicable for ADL-P SoC.
Hence recommendation is to keep it disabled.

BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of c1-state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.

Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-15 18:11:37 +00:00
MAULIK V VAGHELA 99356386a6 soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.

This patch hooks up this parameter to devicetree

BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Check code compiles and correct value has been passed to FSP.

Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15 18:11:16 +00:00
MAULIK V VAGHELA 215a97ee1c soc/intel/adl/chip.h: Convert all camel case variables to snake case
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.

By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.

During renaming process, this patch also removes unused variables
listed below:
-> SataEnable   // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used

Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.

BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.

Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15 18:10:41 +00:00
Eloy Degen 6207a3967e Documentation/tutorial/part1.md: Add Fedora package `patch`
It is necessary to build crossgcc.

Change-Id: I32f6507b4d8346bf94aaccd3eef4f22697c33965
Signed-off-by: Eloy Degen <degeneloy@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15 11:18:31 +00:00
Subrata Banik 4703edc943 {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.

This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:18:28 +00:00
Subrata Banik 47b836af96 soc/intel/common: Pass `FSPM_UPD *` argument for spd functions
This patch adds `FSPM_UPD *` as argument for
mem_populate_channel_data() and read_spd_dimm().

This change will help to update the architectural FSP-M UPDs in
read_spd_dimm().

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:17:38 +00:00
Subrata Banik 2eb51aace5 {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.

This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:17:25 +00:00
Shelley Chen 5730d018d1 mb/google/herobrine: consolidate hoglin/herobrine QUP inits
Hoglin and Herobrine (proto1) should share majority of GPIOs.
Conslidating the QUP initializations in mainboard.  Also, putting
fingerprint init in a conditional as not all devices will have an FP
sensor.

BUG=b:182963902,b:223826899
BRANCH=None
TEST=booted BIOS on hoglin and check for i2c errors in dmesg

Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14 22:28:56 +00:00
Mars Chen d99e773460 mb/google/trogdor: Add variant Gelarshie
New board introduced to trogdor family.

BUG=b:223101874
BRANCH=none
TEST=make

Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com>
Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14 22:04:26 +00:00
Patrick Georgi 46213f6bbe Documentation: Describe our Coverity Scan integration
Change-Id: I0a2b68a4b4b54c7345280b252d624799316641b1
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-14 19:02:32 +00:00
Felix Singer cf4a3472b9 payloads/seabios: Update stable version to 1.16.0
SeaBIOS 1.16.0 was released on March 2nd. Thus, update the stable
version from 1.14.0 to 1.16.0.

Change-Id: I475a9be47171bfbe3b3c2d4d1d14bb753d8575a8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-03-14 18:18:42 +00:00
Casper Chang f7abb4fccf mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.

BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
     scope enable pin while performing suspend stress and enable pin
     works as expected.
     test suspend stress 1000 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 16:18:52 +00:00
Sean Rhodes 13f49ce754 mb/starlabs/labtop: Pull SSD Pin to low when entering S3
Pull GPP_D16 to low when suspending, otherwise it will remain active
and use power.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14 15:57:16 +00:00
Werner Zeh 06fe5d565d mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
DDR4 SPD data needs to be 512 byte to comply with the spec.

Though there is no vital timing data used beyond 256 byte there are some
part information which will be used to show the part info in the
coreboot log. If the buffer is too small this log shows garbage.

This patch increases the SPD buffer size from 256 byte to 512 to avoid
side effects.

Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14 15:53:54 +00:00
Patrick Rudolph ceecc485b0 MAINTAINERS: Remove myself
Change-Id: Ie75912698e58088ff4a334403cb331542abb40fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62754
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:53:10 +00:00
Sridhar Siricilla 282c2a6472 soc/intel/common: Use generic enum type values
The patch uses generic enum type values for EOP command handler. So,
it renames cse_eop_result enum type to cse_cmd_result and also renames
the enum values to have generic name.

TEST=Build the code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:45 +00:00
Sridhar Siricilla 1506b77b60 soc/intel/common: Use heci_reset() in the CSE TX and RX flows
The patch implements error handling as per the ME BWG guide. The BWG
recommends HECI interface reset if there is a timeout or malformed
response is received from the CSE. Also, the patch triggers HECI
interface reset if the CSE link state is not ready in the heci_send()
API.

TEST=Verify HECI Interface reset in the simulated error scenarios.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:29 +00:00
Sridhar Siricilla 6836da2e5a soc/intel/common: Implement error codes for for heci_send_receive()
The patch implements below changes:
1. Implements different error codes and use them in appropriate
 failure scenarios of below functions:
  a. heci_send()
  b. recv_one_message()
  c. heci_receive()

2. As heci_send_receive() is updated to return appropriate error codes
 in different error scenarios of sending and receiving the HECI
 commands. As the function is updated to return 0 when success, and
 non-zero values in the failure scenarios, so all caller function have
 been updated.

BUG=b:220652101
TEST=Verified CSE RX and TX APIs return error codes appropriately in
the simulated error scenarios.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:12 +00:00
Dtrain Hsu 4b8079152a mb/google/brya/var/kinox: update overridetree
1. Update override devicetree based on schematics.
2. ALC5682I-VS is for audio codec.

BUG=b:218786363, b:214025396, b:212183045
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:49:43 +00:00
Raul E Rangel b52b7010ef mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCK
The verstage.c file contains PSP verstage specific code. We don't need
it when using x86 verstage.

BUG=b:193050286
TEST=Build and boot guybrush with x86 verstage

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:48:57 +00:00
Cliff Huang 938f33e9f7 mb/google/brya: Set EPP to 45% for all Brya variants
This sets EPP value to be 45% for all Brya variants.

Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.

BUG=b:219785001
BRANCH=firmware-brya-14505.B
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:48:29 +00:00
Cliff Huang 0bb2225718 soc/intel/alderlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.

BUG=b:219785001
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:48:11 +00:00
Teddy Shih ca9658bdb2 mb/google/dedede: Update DPTF setting
Update PL1, PL2, and temperature sensor values from thermal team,
as well as, we remove unused temperature sensors according to
baseboard/devicetree.cb and mainboard schematic. After we check
DTT setting, the thermal and performance test pass.

BRANCH=dedede
BUG=b:204229229
TEST=on beadrix, run following commands:
localhost /tmp # cat /sys/class/thermal/thermal_zone*/type
x86_pkg_temp
INT3400 Thermal
TSR0
TSR1
TCPU
localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp
45000
20000
32800
32800
39000

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:50 +00:00
Felix Held ae7ec18d3d mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2
The one USB2 port on the XHCI2 controller should have the port ID 2.0,
since it's the first USB2 port on that XHCI controller.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a370132960939bccec4eb69a6590d0880b04137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:21 +00:00
Felix Held b0d555733a mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
GFX HDA is the audio controller that provides audio output via the
external display connection, ACP is the audio coporcessor for the on-
board audio codec and XHCI2 is the third XHCI controller that provides
one USB 2.0 port. All those devices are used, so enable them in the
board's devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:07 +00:00
Eric Lai e6f71a5d28 mb/google/nissa/var/nivviks: Hook up SD host controller GL9750
Select GL9750 driver and add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.

BUG=b:223304292
TEST=check GL9750 can get enumerated by kernel 5.15.
01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01)

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-14 15:46:49 +00:00
Eric Lai 232dcb938a mb/google/nissa/var/nivviks: Enable pen garage
Enable pen garage. Pen detect is active low. And wake system when
eject.

BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
  Event type 0 (EV_SYN)
  Event type 5 (EV_SW)
    Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-14 15:46:24 +00:00
Martin Roth 25c717d664 Documentation: Fix broken links
This change mostly changes  links that were identified as broken by
the 'website_scans' jenkins job.

There were some links that seem to be up at times, but that are
identified by link-checker as broken because of SSL issues.

At least one other link was changed to point to archive.org so
that it doesn't break at some point in the future.  We should
probably try to make sure that everything is archived there and
point to those versions when possible.

There are still lots more links to do.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-14 15:38:20 +00:00
Felix Singer d55fa332d8 Documentation: Move firmware flashing tutorial to tutorial section
There is no need that the tutorial for flashing firmware has its own
point in the main menu. Thus, move it to the tutorial section.

Change-Id: Ife6d97254af4c006fe01480a78c76303f9cb34bb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
2022-03-11 19:56:22 +00:00
Felix Singer c664056c56 Documentation: Use file paths to flashing firmware tutorial
In preperation for CB:62424, replace HTTP links pointing to the flashing
firmware tutorial with file paths to the Markdown files.

Change-Id: I6a271a912348cbe002bc9cced9922ed743e1133c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-11 19:39:44 +00:00
Felix Singer c774a93bcf docs/contributing/gsoc: Add a collection of useful GSoC links
Change-Id: Ia0a1564f41d796ce86179d06b1d0b64021dc0a43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62660
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-11 09:15:43 +00:00
Cliff Huang 5069f6c3c8 drivers/pcie/generic: Add support to generate code under companion device instead
Only one ACPI device should be added to a PCIe root port. For the root
ports which already have device created, the generated code from this
driver needs to be merged with the existing device.

By default, this driver will create new device named DEV0.
This change allows to generate code under an existing device.

ex: (generate code under PXSX):
    Scope (\_SB.PCI0.RP01.PXSX)
    {
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
            Package (0x01)
            {
                Package (0x02)
                {
                    "UntrustedDevice",
                    One
                }
            }
        })
    }

BUG=b:221250331
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10 23:57:16 +00:00
Julius Werner ce87832c66 cbmem: Fix console banner matches
Since the new loglevel markers were added, there will now be a marker
character at the beginning of the coreboot banner string, and this will
make the existing regular expressions meant to find it fail to match.
This patch fixes the problem by just allowing for a single extra
character there (any character to avoid the hassle of having to match
the marker explicitly). The extra character is optional so that we will
still continue to match banners from older versions of coreboot as well.

Since the `?` glyph is not available in basic POSIX regular expressions,
we have to switch to REG_EXTENDED syntax (should otherwise make no
difference). (Also, move side effects out of assert() while I'm here,
that's not actually safe for the standard libc implementation.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62720
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 23:42:53 +00:00
Bora Guvendik 860672e987 soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table after normalizing to the zero-point value. Although
consumer CSE sku also supports this feature, it was validated on
CSE Lite sku only.

BUG=b:182575295
TEST=Able to see TS elapse prior to IA reset on Brya/Redrix

990:CSME ROM started execution                        0
944:CSE sent 'Boot Stall Done' to PMC                 88,000
945:CSE started to handle ICC configuration           88,000 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC             90,000 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC   282,000 (192,000)
  0:1st timestamp                                     330,857 (48,857)
 11:start of bootblock                                341,811 (10,953)
 12:end of bootblock                                  349,299 (7,487)

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10 23:23:13 +00:00
Jon Murphy 9df0085193 mb/google/skyrim: Configure WLAN
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN.  Mappping derived from Skyrim schematic.

BUG=b:214412172
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 23:22:33 +00:00
Jon Murphy d42d8ea0a2 mb/google/skyrim:Update GPIO 32
GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin

BUG=b:214412172
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 23:21:49 +00:00
Ravi Kumar Bokka 9b2914fe62 mb/google/herobrine: Add trackpad initialization
Initialize trackpad on Qualcomm reference boards

BUG=b:182963902,b:223826899
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I93e866d92cf37887a98de88b4b2d768562515670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62226
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 18:19:59 +00:00
Raul E Rangel f63dd17bb1 mb/google/guybrush: Enable DEBUG_SMI for non-serial firmware
In order to copy the PSP verstage logs into x86 cbmem, we need to enable
DEBUG_SMI. This will include the CBMEM console code in SMM. I only
enable DEBUG_SMI when UART is disabled because SMM doesn't currently
save/restore the UART registers. This will result in clearing the
interrupt enable bits and makes it so you can no longer use the TTY.

BUG=b:221231786, b:217968734
BRANCH=guybrush
TEST=Build serial and non serial firmware and verify DEBUG_SMI is set
correctly.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:24:06 +00:00
Raul E Rangel 54786fece8 soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.

replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.

I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.

BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:23:35 +00:00
Raul E Rangel e6cd6caf31 cpu/x86/smm: Add weak SoC init and exit methods
This change provides hooks for the SoC so it can perform any
initialization and cleanup in the SMM handler.

For example, if we have a UART enabled firmware with DEBUG_SMI, the UART
controller could have been powered off by the OS. In this case we need
to power on the UART when entering SMM, and then power it off before we
exit. If the OS had the UART enabled when entering SMM, we should
snapshot the UART register state, and restore it on exit. Otherwise we
risk clearing some interrupt enable bits.

BUG=b:221231786, b:217968734
TEST=Build test guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I946619cd62a974a98c575a92943b43ea639fc329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:06:51 +00:00
Kevin Chiu 496734379d mb/google/guybrush/var/nipperkin: turn off WWAN DPR
Sets GPIO 42 to high to turn off WWAN DPR

BUG=b:216735313
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     make sure GPIO42 is high

Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10 15:18:55 +00:00