Commit Graph

261 Commits

Author SHA1 Message Date
Patrick Georgi 7aa44522f2 3rdparty/fsp: update to current master
This includes the SplitFspBin.py script.

Change-Id: I6323a7a1a2bd9b5e11c0b21e5ea991a3fbd3daac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-05 03:29:25 +00:00
Patrick Georgi f585141cb9 submodules: add FSP mirror as non-default submodule
Like the 3rdparty/blobs repo this isn't checked out by default. Right
now you can manually check it out using

    $ git submodule init --checkout

A follow up commit will add some automagic if USE_BLOBS and
MAINBOARD_USES_FSP2_0 are enabled.

Change-Id: Ie612495abc2a2d5947225e6ab54872aa72d4bec6
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/28303
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02 03:07:50 +00:00
Patrick Rudolph a93d22dd58 3rdparty/blobs: Update submodule pointer to pull in latest changes
* Include Cavium's CN81xx BL31.elf
* mainboard/google: Add folder kahlee for video binary
* Stoney Ridge: PSP bootloader update
* cpu/intel: remove microcode header files for model_306ax

Change-Id: Ie8f3b2e8db0692e95caee245733054e4e20f61ea
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-27 03:00:43 +00:00
Paul Menzel fafc11f2f5 3rdparty/blobs: Update submodule pointer to include latest AMD ucode
The two commits below are added to the BLOBs repository.

*   fe7c6a3 pcengines/apu2: Disable ECC Exclusion range
*   3854ad2 cpu/amd/family_15h: Add latest AMD ucode file

The latest AMD microcode patches include Spectre mitigations.

Change-Id: I4729cc054fe8267549d7369cea4d26aa51861e1c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02 07:41:03 +00:00
Arthur Heymans b00bac707f 3rdparty/libgfxinit: Update submodule pointer
Update to current master.

This includes:
- G45 support
- fixes scaling on eDP (needed for working textmode on eDP)
- gfx_test drawing and moving cursors
- Adding support for Tiling on <= Haswell
- Allow changes to the framebuffer configurarion without resetting the
pipe.

Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26823
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08 03:27:23 +00:00
Nico Huber 514bd56af9 3rdparty/libgfxinit: Update submodule pointer
Update to current master. Beside a minor workaround for GCC 8
compatibility, this includes only refactorings and preparations
for G4x support.

Change-Id: I6b2aa6bd9d41b852dacd8e1dfe89d92c8a548121
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26420
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23 12:43:03 +00:00
Patrick Georgi 2e8b770a9e 3rdparty/chromeec: Update to latest master
Includes the necessary changes to build with gcc 8.1

Change-Id: Ie8c3dede4d702ab7838162dbff09f94df34b7c91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-23 12:02:58 +00:00
Nico Huber 466841e723 3rdparty/libhwbase: Update submodule pointer
Pull a minor update for GCC 8 compatibility.

Change-Id: I0a4af47d56f3ca0b8ed82533e84c44041661ca35
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26306
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22 07:12:43 +00:00
Martin Kepplinger e397f55702 3rdparty/blobs: Update submodule marker for Intel microcode updates
This adds the following changes to the blobs repository:

78a02a7 cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models

In short: Bump Intel microcode updates. They include spectre/meltdown
mitigations.

Change-Id: I141f4446bc4e3bff5641bc39b70b299dc09ac8a7
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/26270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-15 13:19:19 +00:00
Nico Huber e100fe4a59 Revert "3rdparty/blobs: Update submodule marker for Intel microcode updates"
This reverts commit 0ff9daac45.

It points to a stale commit under review; i.e. not to a commit on
blob.git's master branch like it's supposed to.

Change-Id: I19cb8a32b3971c3104e381673ca08ae4d3979128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-12 20:17:02 +00:00
Martin Kepplinger 0ff9daac45 3rdparty/blobs: Update submodule marker for Intel microcode updates
This moves the blobs submodule marker forward to include the following:

b45abbd cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models

in short: bump Intel's microcode updates to the latest version. This
includes Spectre/Meltdown mitigations.

Change-Id: I4ab74ae0bdcf2a109b0697ad233fbb812b5c4544
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/25505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 06:33:43 +00:00
Duncan Laurie cab643e472 Update vboot submodule to upstream master
Updating from commit id e0b38418:
- image_signing: Add sha1sum of keys in keyset to VERSION.signer.

To commit id 392211f0:
- Update Android signing to support signature scheme v2

This fixes bulding with depthcharge master.

Change-Id: I07b570f54b26a937a5a7c53ade464e0c7a550312
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26 16:35:16 +00:00
Nico Huber 0beb62760d 3rdparty/libgfxinit: Update submodule pointer
Update libgfxinit to current master. Changes include:

* a fix to decode the size stolen memory correctly on pre-SandyBridge
  hardware,
* a PCI id based generation check, obsoleting the old check based
  on PCH audio ids,
* some minor improvements around rarely used DDI ports (D and E), and
* added support for tiled and rotated framebuffers on Skylake+ hardware
  (less interesting for coreboot, I guess?).

TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6
     (Skylake) both with text and linear framebuffers and observed
     FILO's prompt showing up.

Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25453
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:42:48 +00:00
Richard Spiegel 013f1024c3 stoneyridge: Update AGESA binary and AGESA.h
AGESA.bin was updated in the binary repo, so update the submodule pointer.
Among other changes, this added a callback "AGESA_HALT_THIS_AP", which
requires updated header files.

BUG=b:70338633
TEST=build kahlee.

Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25183
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-16 19:01:30 +00:00
Martin Roth 13089b008f Update chromeec submodule to upstream master
Updating from commit id 9fb10386a: 2017-06-21 04:19:06 -0700
(Poppy: Configure camera PMIC to low power mode.)

to commit id 927b64a0b: 2018-02-15 00:10:45 -0800
(meowth: zoombini: enable CONFIG_CMD_PD_CONTROL)

This brings in 1205 new commits.

Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 10:03:22 +00:00
Marc Jones 3e9694ef48 Update blobs submodule to upstream master
Updating from commit id a5efee5:
2018-01-04 16:24:19 -0700 - (Kahlee/Grunt: Move remaining stoneyridge blobs)

to commit id 19dea8d:
2018-02-01 08:51:06 -0700 - (soc/amd/Stoneyridge: Update PSP binaries to AGESA 1.3.0.9)

This brings in 2 new commits.

Change-Id: I7858ad8be13d9992949effb0216723d2480fa74d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23562
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-02-05 19:51:22 +00:00
Julius Werner 98d2d3940e Update arm-trusted-firmware submodule to current upstream master
This patch updates the arm-trusted-firmware submodule from:

commit 9fd4a36c408a254d887106e6e3960d496456be2c
(Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)

to

commit 693e278e308441d716f7f5116c43aa150955da31
(Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch)

This brings in 79 new commits.

Change-Id: Ieceb07760178f8ddbb5cafebabeb78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02 22:18:49 +00:00
Richard Spiegel 4eaf0fa155 src/soc/amd/stoneyridge/Kconfig: Use vbios new location
3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into
soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated
to use VBIOS.bin new location.

BUG=b:70785272
TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should
fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it
should work (need to rebuild .config first).
CQ-DEPEND=CL:881709

Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25 16:33:08 +00:00
Martin Roth e6108b2ce3 Update vboot submodule to upstream master
Updating from commit id f6780a36:
2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge)

to commit id e0b38418:
2018-01-16 04:08:26 -0800 - (image_signing: Add sha1sum of keys in keyset to VERSION.signer.)

This brings in 25 new commits.

Change-Id: If60f19decd91eaafec1d555c1e7d3ca0249d8068
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23 22:57:57 +00:00
Martin Roth feb0883a3b Update arm-trusted-firmware submodule to upstream master
Updating from commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)

to commit id 9fd4a36c:
2018-01-17 17:34:29 +0000 - (Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)

This brings in 596 new commits.

Change-Id: Icbe7ede1583f715f3e30bf013df6ba164319e3a1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-23 22:57:49 +00:00
Richard Spiegel a98727849a 3rdparty/blobs/soc/amd/stoneyridge: Use new location of stoneyridge blob
Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were
moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob
to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it.

BUG=b:69613465
TEST=Build and run kahlee.

Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-07 18:36:30 +00:00
Nico Huber 82049cb850 drivers/intel/gma: Power up legacy VGA block early
This is required at least on Skylake to be able to configure text mode.
3rdparty/libgfxinit is also updated by the single commit:

    42fb2d065d gma: Add procedure to power up legacy VGA block

Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-12 09:20:07 +00:00
Marc Jones 17c354dda9 Update vboot submodule to upstream master
Updating from commit id 3b80572:
2017-10-12 16:35:30 -0700 - (tlcl, tpmc: extend GetVersion to report vendor specific data)

to commit id f6780a3:
2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge)

This brings in 19 new commits.

Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22777
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-09 03:11:11 +00:00
Nico Huber 504d1eff4b 3rdparty/lib{hwbase,gfxinit}: Update to latest master
Simplifies our C interface function gma_gfxinit(), due to the following
changes:

* *libgfxinit* knows about the underlying PCI device now and can
  probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
  library where we validate that we neither overflow
  - the stolen memory,
  - the GTT address space, the GTT itself nor
  - the aperture window (i.e. resource2 of the PCI device)
    that we use to access the framebuffer.

Other changes:

* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
  Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.

TEST=Booted lenovo/t420 and verified that everything works as usual.

Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28 19:46:17 +00:00
Daisuke Nojiri 6370e7dfc1 Update vboot submodule to upstream master
Updating from commit id a52fc548
(image_signing: Remove legacy unified build feature)

to commit id 3b805725
(tlcl, tpmc: extend GetVersion to report vendor specific data)

This brings in 22 new commits.

Change-Id: I51e44490e0ffd2c5cc73d439c1f3f8831d816be9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22 01:47:34 +00:00
Daisuke Nojiri c6dcdbfe19 Update vboot submodule to upstream master
Updating from commit id 3f3a496a 2017-09-01 09:20:19
(image_signing: Fix loem.ini pattern for unibuilds)

to commit id 753e34e9 2017-08-31 10:12:40
(futility: Make rwsig sign command produce EC_RW image)

This brings in 5 new commits.

This also updates Depthcharge stable commit ID.

Updating from a843f262 2016-08-16 08:41:04
(kahlee: select emmc boot first if available)

to commit id f3bb31fe 2017-08-15 17:15:33
(vboot: Support EC early firmware selection)

This brings in 14 new commits.

Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13 02:24:37 +00:00
Patrick Georgi 2997a97a3a 3rdparty/vboot: update to latest master
Besides some internal changes that won't have much effect on coreboot,
the newer version also supports building host tools on systems that
self-designate as i686.

Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06 08:24:04 +00:00
Martin Roth 66dce275e5 Update vboot submodule to upstream master
Updating from commit id 8b714252 - 2017-07-18 02:36:16
(crossystem: Remove defunct sw_wpsw_bootfield)

to commit id 8c4b8285 - 2017-08-14 20:37:45 -0700
(detachables: Skip "Enable Developer Mode" in DEV mode)

This brings in 6 new commits.

Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-23 16:32:52 +00:00
Martin Roth 6c1c9d5d5f Update vboot submodule to upstream master
Updating from commit id 04b3835b:
2017-06-12 06:47:41 -0700 - (Add a script to generate a keypair for signing Rose RW firmware.)

to commit id 8b714252:
2017-07-18 02:36:16 -0700 - (crossystem: Remove defunct sw_wpsw_boot field)

This brings in 19 new commits.

Change-Id: Ib68068b1afc5a264623021325e19644e8b63f8f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-31 20:30:55 +00:00
Martin Roth 8f1e1bd44d Update arm-trusted-firmware submodule to upstream master
Updating from commit id 3944adca:
2017-03-18 12:16:27 +0000 - (Merge pull request #861 from soby-mathew/sm/aarch32_fixes)

to commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)

This brings in 373 new commits.

Change-Id: I653007f664921305d22645f7904bb2d8eb85fe67
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-31 20:30:51 +00:00
Martin Roth 07cca22c22 3rdparty/chromeec: Update submodule to upstream master
Update from commit bcffec7fd - reef: Cleanup battery code
to commit 9fb10386a - Poppy: Configure camera PMIC to low power mode.

Brings in 794 new commits from Jan 2, 2017 to Jun 21, 2017

Change-Id: I864679360bd3b211b6883a662e20812b49aefbba
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27 16:06:31 +00:00
Martin Roth f3ed7c1a34 3rdparty/blobs: Update submodule
Update blobs pointer to bring in the AGESA.bin changes for
amd/00670F00/FP4 and amd/00670F00/FT4.

Change-Id: I739124090e41edaf76210cda6189b2c7545cdf58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27 01:11:22 +00:00
Martin Roth 8b388e4741 Update vboot submodule to upstream master
Update from commit a1c5f7c0
vboot_reference: Add support for 3072-bit exponent 3 keys

to commit 04b3835b
Add a script to generate a keypair for signing Rose RW firmware

This brings in 34 new commits.

Change-Id: Ifa304af5c2cf0bcc466dfc4878dd9d08436eec75
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-17 19:58:40 +02:00
Nico Huber eb881d46e2 3rdparty/libgfxinit: Update submodule pointer
Update libgfxinit to the latest master. Changes:

* Remove trailing whitespace in debug output.
* Change some types to make it verify with SPARK Pro.
* Add Broxton (Apollo Lake) support for eDP/DP/HDMI.
* Add Linux user-space test tool `gfx_test`.
* Add a README describing libgfxinit and the build process.

TEST=Booted lenovo/t420 and verified that internal and
     external displays are working.

Change-Id: I4d0e23b8a254234173461b831585eae58d3af58e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-08 14:15:19 +02:00
Nico Huber 7b79a338bd 3rdparty/libhwbase: Update submodule pointer
Update libhwbase to the current master. Some noteworthy changes:

* Add prerequisites for upcoming Apollo Lake support in libgfxinit.
* Add some support for Linux user-space for libgfxinit's `gfx_test`.
* Fix compilation with GCC 7.

Change-Id: If3c65065ef9a2ff6fce221939fda43c9e30c1eb8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-08 14:14:45 +02:00
Martin Roth 76b8c0e044 3rdparty/arm-trusted-firmware: Update to upstream master
Submodule 3rdparty/arm-trusted-firmware 236c27d21f..3944adca59

This brings in 241 new commits from the upstream arm-trusted-firmware
repository, merged to the upstream tree between December 30, 2016 and
March 18, 2017.

3944adca Merge pull request #861 from soby-mathew/sm/aarch32_fixes
..
e0f083a0 fiptool: Prepare ground for expanding the set of images at
runtime

Also setup ATF builds so that unused functions don't break the build.
They're harmless and they don't filter for these like we do.

Change-Id: Ibf5bede79126bcbb62243808a2624d9517015920
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18 23:55:48 +02:00
Nico Huber 989aae9f61 3rdparty/libgfxinit: Update submodule pointer
Some renamings force us to update our code:

  * Scan_Ports() moved into a new package Display_Probing.

  * Ports Digital[123] are called HDMI[123] now (finally!).

  * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.

Other noteworthy changes in libgfxinit:

  * libgfxinit now knows about ports that share pins (e.g. HDMI1 and
    DP1) and refuses to enable any of them if both are connected
    (which is physically possible on certain ThinkPad docks).

  * Major refactoring of the high-level GMA code.

Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08 13:02:44 +02:00
Marshall Dawson 3c645391c0 3rdparty/blobs: Update for AMD Stoney Ridge
Add the binaryPI file for the FT4 package and add SMU firmware to
be consumed by fanless OPNs.

Change-Id: I1c9b5ded6b494fac1553cc2ec7756a7a47386ecf
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18988
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28 22:33:14 +02:00
Martin Roth ba2531c8a2 3rdparty/vboot: Update to upstream master
This brings in 70 new commits from the upstream vboot repository,
dated October 31, 2016 to March 2, 2017

Change-Id: Iac9c2b0389afbfa02c1cccc38d39a12dac4a5ac4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18953
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-27 02:57:08 +02:00
Martin Roth f34ca46fa6 3rdparty: update arm-trusted-firmware submodule
Updated to arm-trusted-firmware TOT:
236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size)
183 commits between Sep 20, 2016 and January 10, 2017

- Also add associated change to src/soc/rockship/rk3399 Makefile.inc
that is required to build the M0 Firmware.

Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-12 18:38:26 +01:00
Martin Roth 74e0b2795f chromeec: Update Chrome EC submodule
Update to Chromium TOT with bcffec7f (reef: Cleanup battery code)

292 commits between Oct 28, 2016 and Jan 2, 2017

Change-Id: I6bc356b9e458bebaa5839375ff40dd7e0d6ccff1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18023
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-10 17:23:37 +01:00
Nico Huber f971dcbf25 3rdparty/libgfxinit: Update to latest master
Changes:

  o Verification that the framebuffer matches the display mode

  o Automatic upscaling if the framebuffer resolution is lower
    than the display mode's

  o VGA-plane support

  o HDMI pixel rate is limited to hardware constraints

  o Error tolerant handling of EDID header-pattern

Change-Id: Icbfdf5f37caf99f66847a71f784730aced0826ab
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17775
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-15 23:47:53 +01:00
Marshall Dawson 2ab96fc955 3rdparty/blobs: Update for AMD Stoney Ridge
Update the blobs submodule to bring in the binaries for 00670F00.
This also corrects some formatting in the various license.txt files.

Change-Id: I7a70d1168734d06ef6919d83dd73bc8f2bc4173c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17872
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins)
2016-12-15 00:37:09 +01:00
Nico Huber 542e9488bd drivers/intel/gma: Hook up libgfxinit
Add `libgfxinit` as another option for native graphics initialization.
For that, the function gma_gfxinit() (see drivers/intel/gma/i915.h) has
to be called by the respective northbridge/soc code.

A mainboard port needs to select `CONFIG_MAINBOARD_HAS_LIBGFXINIT` and
implement the Ada package `GMA.Mainboard` with a single function `ports`
that returns a list of ports to be probed for displays.

v2: Update 3rdparty/libgfxinit to its latest master commit to make
    things buildable within coreboot.

v3: Another update to 3rdparty/libgfxinit. Including support to select
    the I2C port for VGA.

Change-Id: I4c7be3745f32853797d3f3689396dde07d4ca950
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-29 23:46:05 +01:00
Nico Huber c83239eabc Hook up libhwbase in ramstage
It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`.

This also adds some glue code to use the coreboot console for debug
output and our monotonic timer framework as timer backend.

v2: Also update 3rdparty/libhwbase to the latest master commit.

Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16951
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-29 23:45:40 +01:00
Furquan Shaikh 06eee265c2 3rdparty/vboot: update to latest master
Require new recovery reason for rec hash space lock failure in RO.

Change-Id: I606d1a1f51a3a4c127b2933f6fb00ba2ec4885fc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17340
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-10 00:57:27 +01:00
Nico Huber ef405a2c04 Set up 3rdparty/libgfxinit
`libgfxinit` is a SPARK library for graphics modesetting. It supports
Intel integrated graphics only, strictly speaking, the Core i processor
line.

Change-Id: Idf4b0e5fbf37a5d974075b2e44d1fa16dc428da3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16949
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-29 01:35:03 +02:00
Nico Huber e09f8acdad Set up 3rdparty/libhwbase
`libhwbase` is a SPARK library that contains some basic support for i/o
access, debugging, timers. Just what I put around `libgfxinit`, to make
it build standalone.

Change-Id: I1918680c14696215522e1c5dae072235bb4e71a3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16948
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-29 01:34:45 +02:00
Duncan Laurie 6733e7d54f chromeec: Update Chrome EC submodule
Update to Chromium TOT with ea1a8699e96425806abdd532d04da254ae093f6e

Change-Id: I28b9f415a4d55442c294abd27c344a91608a06c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-29 01:24:47 +02:00
Duncan Laurie 11afdbf67c chromeec: Update submodule
Update the chromeec submodule to current Chromium TOT.

Change-Id: Ia3d913703fdea0ece02074d8e2d4b30d97e9a97c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17179
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-28 18:59:55 +02:00
Martin Roth 8337a3867b 3rdparty/vboot: update to latest master for rotor support
This pulls in the bdb support for futility so that rotor can build.

Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17061
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2016-10-21 19:39:00 +02:00
Lin Huang 7d8ccfb9b3 google/gru: pass the gpio power supply enable pin to bl31
We need to disable some regulators when the device goes into suspend.
This means that we need to pass some gpios to bl31, and disable these
gpios when bl31 runs the suspend function.

BRANCH=None
BUG=chrome-os-partner:56423
TEST=enter suspend, measure suspend gpio go to low

[pg: also update arm-trusted-firmware to match]

Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70
Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/374046
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07 17:09:02 +02:00
Martin Roth 5a859517e2 3rdparty/blobs: Update to get AGESA binary for pcengines/apu2
The AGESA binary for PC Engines' APU2 board was just added to the blobs
directory.  Update the submodule pointer to allow access.

Change-Id: Ic2995f253d12d17e229526cb71dea5bf65fa36f9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16253
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-08-21 21:20:13 +02:00
Patrick Georgi 88a25ec20a 3rdparty/vboot: update to latest master
Half a year has passed. Fixes went in. Probably bugs, too.
However, nobody really supports our local vboot version anymore.

Change-Id: I5042f23686dfe98e540c482f744e9df2d7df3b19
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16055
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
2016-08-04 23:22:36 +02:00
Martin Roth 935a4303d7 3rdparty/chromeec: Update submodule to latest
From: 388a7fa8 (Wed, 10 Feb 2016)
CR50: remove incorrect output length check in RSA decrypt

To: 83b6d697 (Mon, 1 Aug 2016)
g: increase usb console TX buffer size to 4K

676 commits

Change-Id: Ic80de8b6fd6d9eba2a092b1a3493931241a2e48b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16021
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02 20:06:07 +02:00
Martin Roth 75ced9a123 3rdparty/arm-trusted-firmware: Update to Jun 8, 2016 master
90 patches pulled in.

Change-Id: I3b893957cbd330e71d0f218262e768f577df4c66
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15122
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:14:06 +02:00
Patrick Georgi c84e2fe893 3rdparty/blobs: add more Qualcomm stubs
Change-Id: Ie57b0b7844f28671b8d6a8efe9231a47bfb8f805
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14745
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10 21:22:28 +02:00
Patrick Georgi 30554c8416 3rdparty/arm-trusted-firmware: update to current master
It includes support for rk3399.

Change-Id: I326ef3dc3021313ee852395c302c076b3e3c8c5e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14732
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 06:50:07 +02:00
Patrick Georgi e355ee26b8 vboot: Update to current master to support S3 resume signalling
This is used in coreboot-side vboot code now, to keep booting from
the same RW section after wakeup - necessary when romstage is in RW
and its use of the RAM init configuration cache may differ between
versions.

Change-Id: Ie531cf3ddc980154f48772b3ff87e23473010721
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/13844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29 20:19:06 +01:00
Patrick Georgi 800e964eef arch/arm64: Compile arm-trusted-firmware with coreboot timestamp
Update ATF codebase to a version that supports passing a timestamp and
fix the format to what it accepts now (including quotes).

This provides reproducible builds.

Change-Id: I12a0a2ba1ee7921ad93a3a877ea50309136ab1ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-18 11:08:01 +01:00
Patrick Georgi 1509c908aa 3rdparty/chromeec: fix build with paths containing "@"
Move submodule forward to a newer upstream master to fix the build on
paths containing "@", as can happen on jenkins.

Change-Id: Ie74012725c379909d5bf631f9cc9969106ca52b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13673
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-11 20:52:26 +01:00
Patrick Georgi ec0b586f92 3rdparty/chromeec: Add Chrome EC firmware sources
Note that this is a manually added commit id (to get the CrEC fixes in
that are necessary for building outside cros_sdk), so it will probably
fail.

Change-Id: Idc15cf268c663ae49b209b92b198c9a4d122c7e3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13546
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-05 10:34:17 +01:00
Patrick Georgi 43e6d6a124 3rdparty/vboot: update to current master
It provides a few extensions to the API that are required, such as
vb2api_check_hash_get_digest()

Change-Id: Ib4d8bdc29751f51f0f7532376175490a0ffd84b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13590
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:30:38 +01:00
Martin Roth 9f656c0316 3rdparty/blobs: Update for latest Carrizo Blobs
Update the 3rdparty/blobs submodule to bring in the latest
CarrizoPI binaries.

Change-Id: I65769ebe7b2aa6508d0d6ab2df34a092751e1078
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12425
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-07 16:10:29 +01:00
Patrick Georgi 5dba15c180 3rdparty/vboot: update to current master
Change-Id: Idc300472f8d8821dd362d6dd075150f285f1d09b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12207
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-10-28 22:28:16 +01:00
Timothy Pearson 24e6d0445c cpu/amd/model_10xxx: Install AMD-provided microcode files in CBFS
Change-Id: I208b012c6b612a94b3bbc8235d5a005028be8bcc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-16 02:41:37 +00:00
Paul Menzel 94020135c8 3rdparty/blobs: Update hash to latest commit in BLOBs repository
Update to commit 832bc6f1 (Remove microcode stored in C-array format),
which is the latest commit in the BLOBs repository.

Building the Lenovo X60 currently fails as the microcode file cannot be
found.

	    CREATE     build/mainboard/lenovo/x60/cbfs-file.wkWhPK.out (from src/mainboard/lenovo/x60/cmos.default)
	make: *** No rule to make target '3rdparty/blobs/cpu/intel/model_69x/microcode.bin', needed by 'build/cpu_microcode_blob.bin'.  Schluss.

Change-Id: I40ebceec299f46c19fd60861d872adcd91df3610
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-11 13:27:53 +00:00
Alexandru Gagniuc 321402bfce 3dparty/blobs: Advance to pull in binary microcode
Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11693
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-09-29 04:49:46 +00:00
Stefan Reinauer e07e0441c2 Move blobs marker forward
b4ade40 via/nano: Move CPU microcode to 3rdparty/blobs
8921cc4 amd/model_fxx: Move CPU microcode to 3rdparty/blobs
1099605 amd/model_10xxx: Move CPU microcode to 3rdparty/blobs
5f5604e Convert microcode to binary

Change-Id: I276537281a01f8497ed87108e66574ec45265f3a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11129
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-07 07:16:27 +02:00
Patrick Georgi c88b8c24d9 vboot: Don't count boot attempts if lid is closed
This can be a problem with freshly updated devices that are periodically
powered on while closed (as explained in the bug report).

In this case, just don't count down. In case of actual errors (where we
want the system to fall back to the old code), this now means that the
retries have to happen with the lid open.

Bump vboot's submodule revision for the vboot-side support of this.

BUG=chromium:446945
TEST=to test the OS update side, follow the test protocol in
https://code.google.com/p/chromium/issues/detail?id=446945#c43
With a servo, it can be sped up using the EC console interface to start
the closed system - no need to wait 60min and plugging in power to get
to that state.

Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10851
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08 19:40:24 +02:00
Stefan Reinauer 5e4d53e12b blobs: move marker
Makes the following changes available:

61d663e blobs: Fix assembler code to allow dropping -Wa,--divide
a6c34a6 AMD Steppe Eagle: add PlatformMemoryConfiguration.h
95b8050 AMD FT3b binary PI: Fix Windows 7 graphics driver hang
c7c816e AMD Kern: remove PspSecureOs_prod_CZ.sbin

Change-Id: Ie8ce8278f72c998b91717658a6fc1d0948c7c50a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07 17:59:19 +02:00
Stefan Reinauer b838469e62 arm-trusted-firmware: update marker
Change-Id: I8dddeead3c23a03803e7d8d5b2bfb8a15c5c2807
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10645
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-06-23 22:27:14 +02:00
Patrick Georgi 2f88b83ed1 submodules: add arm-trusted-firmware third-party repository
Change-Id: I080c0a5954d3e4b2d6debdf2a77f32df7329841c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 08:20:24 +02:00
Marc Jones dbe6ba465e 3rdparty/blobs: Move submodule marker forward
Pick up the latest from blobs.
34b0926 AMD Merlin Falcon: remove build warnings
e581a5c AMD pi: replace LocateModule with agesawrapper_locate_module
c5ddfb6 AMD PI: remove unuseful code

Change-Id: I2b9d2b61cb00aa651b90dc76368d215077e27cad
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10603
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-20 02:35:40 +02:00
Stefan Reinauer 7577c13cb6 3rdparty/blobs: Move marker forward
Change-Id: I2a9304a6b573a10e896f9ff77bfb09f20b21eb50
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10541
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-15 18:39:09 +02:00
Marc Jones 538ce57d47 3rdparty/blobs: Move submodule marker forward
New marker includes:
3d5af98 microcode: Update Broadwell to MC0306D4_0000001F
349fd55 microcode: Update Baytrail to M0C30678_000082D
9077293 Add BLOBs to support AMD Embedded "Merlin Falcon" processor

Change-Id: I53f8f95079c6436ad316a11d432fcf92c03332b5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10506
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-11 19:14:58 +02:00
Marc Jones e7db9dd2a0 3rdparty/blobs: Move submodule marker forward
Move the 3rdparty/blobs marker to include the following:
a710941 amd/pi: Move AGESA cbfs access function to coreboot
63f1db5 AMD avalon: add PSP firmwares

Change-Id: Ie12b273ab9d22ab440b477919e70419b21cb833b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10202
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-05-13 22:55:50 +02:00
Patrick Georgi 29ed46cacc 3rdparty/vboot: Add vboot
This allows providing a verified boot mechanism in the
default distribution, as well as reusing vboot code like
its crypto primitives for reasonably secure checksums over
CBFS files.

Change-Id: I729b249776b2bf7aa4b2f69bb18ec655b9b08d90
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05 22:49:34 +02:00
Patrick Georgi 26e24cc12d 3rdparty: move to 3rdparty/blobs
There's now room for other repositories under 3rdparty.

Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05 22:49:18 +02:00
Patrick Georgi f4f028790a 3rdparty: Move to blobs
To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.

Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05 22:49:11 +02:00
Stefan Reinauer f3c50d4075 3rdparty: move checkout marker forward
Move the 3rdparty marker to blobs.git commit 892a697

Change-Id: I8a51f301e08e49970b4747f004e0752617de8005
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9625
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-04-14 01:09:51 +02:00
Marc Jones 6f713d2c5b 3rdparty: Update submodule to get Tegra 132 binaries
Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8613
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-07 17:50:58 +01:00
Alexandru Gagniuc 422e296d56 3rdparty: Update to latest commit (for Intel microcode)
This pulls in the Intel microcode from blobs, and allows us to move
forward with relocating microcode updates in blobs.

Change-Id: Iaa046cc20c7825aac168a6ed97c87be548634df3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8356
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-27 18:16:15 +01:00
Dave Frodin 790547b39c 3rdparty: Update to latest commit in blobs repository
'blobs' now contains the update for the BaldEagle binaryPI.

Change-Id: I7ed423b17cee926205792223d6355277bedad552
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16 21:31:58 +01:00
Dave Frodin 3e724828b4 3rdparty: Update to latest commit in blobs repository
'blobs' now contains the update for the Mullins binaryPI.

Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8230
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-15 19:21:05 +01:00
Paul Menzel d4b1139e28 3rdparty: Update to latest commit in blobs repository
Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error
occurs) unintentionally reverted commit 16472743 (3dparty: Update to
latest commit in blobs repository).

Apply that commit again:

'blobs' now contains updates which allow binary AGESA to build with
Clang. Pull those in, in anticipation of re-enabling -Werror on Clang
builds.

Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7963
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-28 16:04:03 +01:00
Tom Warren bb932c56f0 nyan*: I2C: Implement bus clear when 'ARB_LOST' error occurs
This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().

Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.

BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.

Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26 19:39:16 +01:00
Alexandru Gagniuc 16472743ef 3dparty: Update to latest commit in blobs repository
'blobs' now contains updates which allow binary AGESA to build with clang.
Pull those in, in anticipation of re-enabling -Werror on clang builds.

Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7884
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-22 06:19:28 +01:00
Paul Menzel 9562834229 3rdparty: Update to latest commit in blobs repository
Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support
binary AGESA release), which is the latest commit in the blobs
repository.

Change-Id: I3d643f7565700272c22b59ed764c3269801f4413
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7595
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-01 08:50:32 +01:00
Marc Jones 1dba8787c6 blobs: Update to IPQ blob commit
Update the 3rdparty repo to the IPQ binary commit

This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c

Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: http://review.coreboot.org/7354
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry picked from commit cfa06c7460)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0
Reviewed-on: http://review.coreboot.org/7437
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-11-11 23:15:41 +01:00
Vladimir Serbinenko 39bbc8cb97 Kconfig: Hide DYNAMIC_CBMEM.
Only one setting actually works (exact value depends on board). So
no need to show it.

Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7359
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-11-09 02:03:24 +01:00
Marc Jones cfa06c7460 blobs: Update to IPQ blob commit
Update the 3rdparty repo to the IPQ binary commit

Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7354
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-08 01:05:03 +01:00
Bruce Griffith 5eb400f084 AMD Steppe Eagle: Update reference to BLOBs repo (3rdparty)
The BLOBs repo has been updated with AMD PI header files, peripheral
BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for
Steppe Eagle, the Steppe Eagle video BIOS, and platform security
processor firmware.

Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-09-01 00:37:16 +02:00
Vladimir Serbinenko 8ecdc9e877 acpigen: Add acpigen_emit_eisaid.
Change-Id: Ib92142a133445018cd152dabe299792ba5f36548
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5240
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 01:24:53 +02:00
Patrick Georgi a151c12329 3rdparty: update to current HEAD
It includes a sandybridge fix.

Change-Id: I84ff1ac1622b10a4a4aa42517bac0c024c386998
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-11 10:57:34 +01:00
Bruce Griffith ed621ada63 AMD Yangtze: Update 3rdparty hash for new blobs
Change-Id: I87de13a7284bc38ac7cf2b18a147323c84a9a5c5
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3780
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-18 20:06:55 +02:00
Stefan Reinauer f73de9b975 Update 3rdparty hash for latest ARM BL1 binaries
Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3740
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-07-10 03:02:05 +02:00
Stefan Reinauer 673762906b Update 3rdparty mark to latest repository
For new systemagent v6 binaries.

Change-Id: I550533fd19c7c5592f3e3c9b514efe2750619c8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3567
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 00:56:55 +02:00
Stefan Reinauer c4dfae835f Update 3rdparty mark to latest repository
For google/stout binaries

Apparently the actual marker got lost in the rebase / change of the
commit message.

Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-15 19:09:08 +01:00
Mike Loptien 7bc153c6ae Eagleheights DSDT: Grant OS control through OSC
Change the OSC method to actually grant control of
PCIe capabilities to the OS instead of granting no
control.  I believe the logic was backwards in the
original commit.  Bits should be set when granting
control and cleared when not granting control.  By
setting the return value to 0x00, we effectively
tell the OS that it cannot control any PCIe
capability.  See section 6.2.9 of the ACPI spec
version 3.0 for more information.

This edit is a duplication of the OSC method that
is in the src/southbridge/intel/bd82x6x/pch.asl
file.

Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 23:44:00 +01:00
Stefan Reinauer ffc13bdb2a Update 3rdparty mark to latest repository
For google/stout binaries

Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2635
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 23:00:49 +01:00
Stefan Reinauer 39d497d5cf Update 3rdparty mark to latest repository
Change-Id: Ied5515a332e3f2f9abbed1c015cad76f7bb4cd9f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-02-22 09:22:41 +01:00
Stefan Reinauer bd5e1a0ff3 Update 3rdparty mark to latest repository
Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-11 21:51:05 +01:00
Stefan Reinauer 9bcab0c72b Update 3rdparty mark to latest repository
Change-Id: I59fca4427345c7e677138b944613a1554d5a8331
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2110
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-01-05 01:31:12 +01:00
Stefan Reinauer 0e81b62638 Update 3rdparty to it's HEAD
Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2025
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12 06:02:46 +01:00
Stefan Reinauer 6446626c1e Use new system agent binaries
Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1879
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-17 00:29:18 +01:00
Stefan Reinauer 2c485180a8 Updated submodule reference
Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: Ibe0e295293aa0f771063f9c0d1d1e6b69f60007a
Reviewed-on: http://review.coreboot.org/1816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 04:21:27 +01:00
Patrick Georgi 552c45cf1f Finally update 3rdparty
Change-Id: Ic85c1411cd8ccb6b3b96459738fbf8d7d9a2ca77
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1242
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-19 13:58:02 +02:00
Patrick Georgi 1db6e2aa19 Add 3rdparty as submodule
The build system will make sure only to fetch this if
desired by the user.

Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-01 00:08:37 +02:00
Ron Minnich 89823fde18 Remove this directory. We've determined that for a number of very good reasons
we want to keep this tree source-only.

Signed-off-by: Ron Minnich <rminnich@gmail.com>
2012-04-14 18:22:54 -07:00
Ron Minnich 90655c83d0 Add the memory reference code binary for sandybridge chipsets
This binary is required for anyone who wishes to build a
sandybridge mainboard.

Change-Id: I779ef5e2b77166b81cb05eada37291368e74fbb6
Signed-off-by: Ron Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/897
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-04-16 01:12:58 +02:00