Commit Graph

38575 Commits

Author SHA1 Message Date
Felix Singer 3c02ed9cb6 MAINTAINERS: Add missing trailing slashes
Add missing trailing slashes so that Gerrit recognizes maintainers
correctly.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I35fcaf41617247e2b86cd6ddd7ee1b319a695797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48137
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 13:46:54 +00:00
Tim Chu 39ea223249 mb/ocp/deltalake: Update SMBIOS type 8 information
Update port connector information for Delta Lake.

Tested=Execute "dmidecode -t 8" to check all the information of
SMBIOS type 8 is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01 08:04:30 +00:00
Subrata Banik f5c3e29bdf ec/google/chromeec/acpi: Make OperationRegion brace align
Inject TAB to make OperationRegion closing brace align with
opening brace.

Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-01 08:00:23 +00:00
Subrata Banik 52fabb1247 mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP
As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ
hence remove the unused GPIO.

Wrong GPIO configuration is causing platform reboot issue on
ADLRVP with Chrome SKU.

Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01 08:00:09 +00:00
Varshit Pandya 5e1d4dd947 mb/intel/adlrvp: Add ASL support for WFC annd UFC
1. Add 2 ports and 2 endpoints
2. Add support for OVTI5675

WFC Cam is on I2C5 and UFC is on I2C1
BUG=None
BRANCH=None
TEST=Build and Boot adlrvp board and able to capture image
using camera.

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47497
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 07:59:52 +00:00
Varshit Pandya e9695f0d70 mb/intel/adlrvp: Configure Camera related GPIO as per schematics
Configure RST and PWR_EN signals for both WFC and UFC

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47496
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 07:59:23 +00:00
Varshit Pandya 1ce5f5827d mb/intel/adlrvp: Update GPIO configuration as per schematics
Configure I2C related GPIO as per ADL-P schematics.
This is based on Revision 0.974 of schematics.

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01 07:58:57 +00:00
Subrata Banik 840679d2c1 mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot
List of changes:
1. Enable Root Port 8 aka 0:0x1c:7
2. Assign free running clock for RP8
3. Apply W/A to get card detected on x1 slot
- Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low

TEST=Able to detect PCIe SD card over x1 slot
localhost ~ # dmesg | grep mmc
[ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA
[ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8
[ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB
[ 3.849158] mmcblk0: p1

Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48080
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 07:52:26 +00:00
Subrata Banik 0f044a5007 mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
List of changes in SPD:
1. SPD Revision (of JEDEC spec)
2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB)
3. MSB -> CAS Latencies Supported, First Byte
4. CAS Latencies Supported, Second Byte
5. CAS Latencies Supported, Third Byte
6. LSB -> CAS Latencies Supported, Fourth Byte
7. Minimum CAS Latency Time (tAAmin)
8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax)
9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin)
10.Cyclical Redundancy Code (0- 125 byte)

TEST=Able to build and boot with updated SPD.

Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01 07:49:58 +00:00
Sridhar Siricilla ae81d59eca mb/intel/adlrvp: Add support for LPDDR5
This patch adds LPDDR5 memory configuration parameters to FSP.

TEST=Able to pass FSP-M MRC training on LPDDR5 RVP.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01 07:49:47 +00:00
Subrata Banik 4cb8776c31 mb/intel/adlrvp: Refactor lpddr4_mem_config structure
List of changes:
1. Initialize dq_map array in a single line
2. Make dqs_map array also in a single line

TEST=Able to build and boot ADLRVP LP4 SKU.

Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48077
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 07:49:32 +00:00
Yu-Ping Wu 3c729487bf Makefile.inc: Alloc .bss* sections for "struct" file type
When the global variable of a "struct" CBFS file is zero (for example,
CB:47696), the binary will appear in the .bss* section in the ELF file
(instead of .data). This results in an empty binary file added to CBFS,
so that file size check will fail when reading it at runtime.

BUG=b:173751635
TEST=emerge-asurada coreboot
TEST=Check sdram-lpddr4x-KMDP6001DA-B425-4GB is non-empty in CBFS
BRANCH=none

Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47903
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01 07:31:22 +00:00
Paul Fagerburg 679b236bed util/mb/google/puff: remove HECI from overridetree
The template for overridetree.cb includes HeciEnabled, which has
been removed from the CNL config struct, so remove it from the
overridetree.

BUG=b:174360951
TEST=`new_variant_fulltest.sh puff` succeeds

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I87f67c53cc75d9ddd40b4960739180a95de6ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-12-01 01:25:17 +00:00
Felix Singer 617150e0ff mb/siemens/chili: Configure GPIOs in gpio.c
Get rid of variant_gpio_table() and configure GPIOs in gpio.c instead
of passing data around.

Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47974
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 23:08:50 +00:00
Felix Singer e8774933d3 mb/siemens/chili: Introduce include folder for header files
Use include folder for header files allowing proper includes.

Change-Id: I80066fb925b918d040062397e633c5d499a50dbe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47973
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 23:08:31 +00:00
Felix Singer 48b80c134a mb/kontron/bsl6: Configure GPIOs using mainboard_ops
Hook up the mainboard_ops driver and configure the GPIOs using .init,
since mainboard_silicon_init_params() is meant for the configuration of
the FSP, not the GPIOs.

Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47850
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 23:08:17 +00:00
Felix Singer 3616e9c3b0 soc/intel/skylake: Fix comment
mainboard_silicon_init_params() is *not* meant for configuring GPIOs. It
should only be used to configure FSP options, which can not be
configured elsewhere.

Change-Id: Ia92d0d173af9c67600e93b473480967304772998
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48008
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 22:20:46 +00:00
Patrick Georgi 36c2ea4a63 util/pgtblgen: Improve compatibility
Fix build on Debian/jessie

Change-Id: I987e7a03441b40ab06ccd54a21e38aac81a1c28d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30 21:51:05 +00:00
Felix Held e2cb8696f0 soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoC
PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in
the corresponding SoC code, so remove it from the SoC's Kconfig and
reanme it in the mainboard's Kconfig to MANDOLIN_LPC.

Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-30 19:17:29 +00:00
Felix Held ffb4652461 soc/amd/picasso: remove unused AMDFW_OUTSIDE_CBFS Kconfig option
The corresponding functionality in the SoC's Makefile.inc was removed in
commit ef3395d990

Change-Id: Iba84d9deb155ce314b3a3588781752b83a21486b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-30 17:55:10 +00:00
Felix Held 0aada3cddb soc/amd: move bootblock inside main SoC directories
There's no need to have the bootblock in its own sub-directory, so move
it to each SoC's main directory to avoid clutter. This makes soc/amd
more consistent with the coreboot code base in src/northbridge,
src/southbridge and src/soc with the exception of src/soc/intel.

Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47982
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 17:54:22 +00:00
Frank Chu de2ba63f47 mb/google/volteer: Create drobit variant
Create the drobit variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:171947885
BRANCH=none
TEST=emerge-volteer coreboot

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 17:40:23 +00:00
Felix Held 3e22cb6e1c soc/amd/common/vboot: use transfer_buffer_valid function
show_psp_transfer_info reimplemented the functionality of
transfer_buffer_valid, so use replace that with a function call.

Change-Id: Ie3d373b10bdb0ab00640dabeea12b13ec25406cc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30 16:29:14 +00:00
Felix Held cd50715e03 soc/amd: move vboot-on-PSP-related functions to common/vboot
Change-Id: I4f07d3ab12116229a13d2e8c02b2deb06e51a1af
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30 16:28:56 +00:00
Felix Held 9900c4f0b0 soc/amd: move vboot bootblock functions to common folder
Change-Id: I9e9fed26a686b8f90797687dd720902be48dae72
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30 16:28:32 +00:00
Felix Held 84eb61c32c soc/amd: move assembly part of non-CAR bootblock to common directory
There will be more files added to the common non-CAR Makefile.inc, so
use an ifeq statement there.

Change-Id: I1f71954d27fbf10725387a0e95bc57f5040024cc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30 16:28:13 +00:00
Felix Held 21cdf0de08 soc/amd/common: introduce SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Add a Kconfig symbol for including the PCIe MMCONF setup function in the
build and select it when SOC_AMD_COMMON_BLOCK_PCI is selected and in the
southbridges call enable_pci_mmconf(), but don't select
SOC_AMD_COMMON_BLOCK_PCI.

Change-Id: I32de7450bff5b231442f9f2094a18ebe01874ee7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47878
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 16:27:52 +00:00
Arthur Heymans 4b84a2c8a2 drivers/intel/fsp2_0: Remove console in weak function
This pollutes the log on all platforms not implementing an override.

Change-Id: I0d8371447ee7820cd8e86e9d3d5e70fcf4f91e34
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48128
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 08:09:13 +00:00
Meera Ravindranath 2ac88f2347 mb/google/dedede: Update Imon slope and Offset Value for Drawcia
Updating Imon slope and offset values as per recommendation of
ODM based on calibaration.
Updating Imon slope to 1.0 and offset to 1.4

BUG=b:167294777
BRANCH=dedede
TEST=Boot dedede platform and confirm values in FSP.

Change-Id: I3eb32218040163f0abef9b8dd4c52efb16289fe7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vinay Kumar <vinay.kumar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-11-30 08:08:59 +00:00
Raymond Chung eee1f4387a mb/google/dedede: Create sasuke variant
Create the sasuke variant of the waddledoo reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.3.1).

BUG=b:172104731
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_SASUKE

Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I29405d63fd266224807e535c3f86a2ad5ab8cdf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-30 08:08:47 +00:00
Mike Banon 4ae881a576 lenovo/g505s: remove the unused and not present devices
Remove the devices unused or not present on this laptop.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I0decad499dfbb5f1e0a189d21f0fca47c80bd490
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-30 08:08:22 +00:00
Frank Chu ae99ea5f08 mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.

BUG=b:173670150
TEST=Verified that I2C5 frequency is between 386-387kHz.

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 08:07:50 +00:00
Tim Wawrzynczak 092813a50c soc/intel/alderlake: Add initial chipset.cb
Similar to the chipset.cb for TGL, this patch gives alias names to all
of the published PCI devices.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 08:07:26 +00:00
Bora Guvendik 2821cb498b include/device/pci_ids.h: Fix device id for gspi2
Device ID for "D18:F6 - GSPI #2" shoud be 0xA0FB

BUG=none
TEST=Boot to OS, verify SSDT

Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0d814170d24ff1b989eceb1d9ebdf6134df85e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48060
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 08:07:00 +00:00
Tim Wawrzynczak c67e3c1a90 soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devices
Change-Id: I6289d2049fbbb6bb532be3d9e2355c563ec98d1b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-30 08:06:13 +00:00
Tim Wawrzynczak f1b4a7c9d4 elog: Add new wake source codes
Tiger Lake introduces new wake-capable devices, including thunderbolt
ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE
macros for each of these types of devices.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-30 08:05:55 +00:00
Frans Hendriks f90056268f util/docker/Makefile: Add missing separator
Build using docker results in error: Makefile:86: *** missing separator.

Add space after ifeq.

Tested: Building Facebook FBG1701 binary.

Change-Id: Ib42abe966e67dac380173ec982c9f6bd4cf074cc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-30 08:05:29 +00:00
Nick Vaccaro b38ca863d9 mb/google/volteer/variant/copano: Add memory part support
Add support for the following 5 LPDDR4x memory parts:
- MT53E512M64D4NW-046 WT:E
- H9HCNNNCRMBLPR-NEE
- MT53D1G64D4NW-046 WT:A
- H9HCNNNFBMBLPR-NEE
- MT53D512M64D4NW-046 WT:F

DRAM Part Name                 ID to assign
-------------------------------------------
MT53E512M64D4NW-046 WT:E       0 (0000)
H9HCNNNCRMBLPR-NEE             0 (0000)
MT53D1G64D4NW-046 WT:A         1 (0001)
H9HCNNNFBMBLPR-NEE             2 (0010)
MT53D512M64D4NW-046 WT:F       0 (0000)

BUG=b:172993397
TEST=none

Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47981
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 08:03:45 +00:00
Nick Vaccaro ace29dff9e lp4x: Add new memory parts and generate SPDs
Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of
available LP4x parts and to the global JSON file containing LP4x parts
and their characteristics.

BUG=b:172993397
TEST=none

Change-Id: I09c6eab640c169dbdb451964967d14a31e314496
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-30 08:03:35 +00:00
Angel Pons 13c50005c5 mb/prodrive/hermes: Use PCH_DEV_SMBUS definition
This allows dropping ugly preprocessor usage from this file.

Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30 08:03:18 +00:00
Angel Pons fe17a8cd6a mb/prodrive/hermes: Encapsulate GPIO setup
Having variants' gpio.c call the `gpio_configure_pads` function results
in an API that does not need to pass data around, which is much simpler.

Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-30 08:02:09 +00:00
Angel Pons 329ebb340b mb/prodrive/hermes: Use C-style comments
Most of the existing comments are C-style already.

Change-Id: I9ca4779f5b0560320e9bce4f33e54766522689f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-30 08:01:57 +00:00
Pratik Prajapati 1e67816961 inteltool: Add support to print TME/MKTME status
Print whether the SOC supports TME/MKTME. If the SOC supports the
feature, print the status of enable and lock bit from TME_ACTIVATE
MSR. -t option prints this status.

Sample output:

If TME/MKTME is supported:
============= Dumping INTEL TME/MKTME status =============
TME supported : YES
TME locked    : YES
TME enabled   : YES
====================================================

If TME/MKTME is not supported:
============= Dumping INTEL TME status =============
TME supported : NO
====================================================

Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I584ac4b045ba80998d454283e02d3f28ef45692d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-30 08:01:38 +00:00
Felix Held 41220cd245 soc/amd/common: add comments and FIXME to Makefile.inc files
Change-Id: Ie347ee508acd900353467b4a3e0a5d1928b110e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47877
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 08:00:19 +00:00
Felix Held 870e44a7b9 soc/amd/common: simplify conditionals in Makefiles
If there are multiple statements that are conditional on the same
Kconfig option, group them and move the condition check around the
statement. If there's only one statement depending on one condition, use
the short form instead.

Change-Id: I89cb17954150c146ffc762d8cb2e3b3b374924de
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47876
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 07:59:55 +00:00
Felix Held 63d36bc733 soc/amd/common/block/cpu: move CAR-specific Makefile to sub-directory
Since there are sub-directories for both the cache-as-RAM case and the
non-CAR case where the RAM is already initialized when the x86 cores are
released from reset, move the CAR-specific parts of the Makefile.inc to
another Makefile.inc in the car sub-directory. Further patches will add
a Makefile.inc to the non-CAR directory.

Change-Id: I43a3039237d96e02baa33488e71c5f24effe8359
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47875
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 07:59:02 +00:00
Angel Pons 5ad4206e72 drivers/intel/i210: Request Bus Master in .final ops
Commit bd31642ad8 (intel/i210: Set bus master bit in command register)
is only necessary because a buggy OS expects Bus Master to be set, not
because the hardware requires Bus Master during initialization. It is
thus safe to defer the Bus Master request into the .final callback.

Change-Id: Iecfa6366eb4b1438fd12cd9ebb1a77ada97fa2f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47401
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: siemens-bot
2020-11-30 07:58:13 +00:00
Angel Pons 45eeae4f8f mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev()
There's one copy of this function for all variants except mc_apl4. Move
one copy into common mainboard.c and exit early if running on mc_apl4.

Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30 07:57:36 +00:00
Angel Pons afb60e7112 mb/siemens/mc_apl1: Simplify is_mac_adr_valid() logic
A MAC address that is neither 00:00:00:00:00:00 nor ff:ff:ff:ff:ff:ff is
considered valid. Instead of using a temporary buffer and memcmp(), use
a single loop that exits as soon as the MAC cannot possibly be invalid.

Change-Id: I2b15b510092860fbbefd150c9060da38aeb13311
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2020-11-30 07:56:35 +00:00
Angel Pons c19a9a5278 drivers/intel/i210: Define MAC_ADDR_LEN
Define and use the MAC_ADDR_LEN macro in place of the `6` magic value.

Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47404
Tested-by: siemens-bot
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-11-30 07:53:22 +00:00