Commit Graph

4601 Commits

Author SHA1 Message Date
Nico Huber 0b2a632005 crossgcc/gnat.patch: Never treat warnings as errors
We used to disable individual warnings that are expected when building
our GCC version with a newer one. Not all warnings can be disabled
indvidually, though, and it's much easier to simply allow warnings.
As a plus, we get the warnings in the log (in case anybody would ever
look into it).

Partially fixes building with host GCC 12.1.

Change-Id: I8fafec4fc49db73b6dba311c775eea2cc92a9b48
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-10 14:08:57 +00:00
Martin Roth 124c418ccf util/util_readme: update to give additional information
Add a note to the top of the util.md document saying not to edit it.

The Documentation/util.md file had been updated to contain additional
information at the bottom.  This copies that information into the file
after it's been created.

Change-Id: I4b08439420ceb706df62e3949406585ea34c1514
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 15:49:56 +00:00
Martin Roth 56846091f1 util, Documentation: Run util_readme.sh to regen util.md
Change-Id: Ie14204d0637bb5081e2fae4a9a0e2590bf7abeeb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 15:49:27 +00:00
Julius Werner 423cd06fa6 cbfstool: Expand CBFS verification validity check
This patch adds a new line to `cbfstool print -v` output that records
the overall CBFS verification health of the image. While this info was
already visible from individual fields before, it's nice to have a
one-stop location to see "this is a good image" without having to
carefully parse a lot of output manually.

Also add a few lines to the Makefile that check whether this field is
valid for the final image (it always should be, but hopefully this check
will allow us to catch regressions like the one fixed by CB:64547 sooner
in the future).

BUG=b:233263447

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1b74b01a55b22294556007aaee835d0fdb9e1c63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-07 12:57:25 +00:00
Michał Żygowski de91780c30 inteltool/gpio_names/tigerlake.h: Fix HVMOS pad count
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I344fd2db9d53ad5e82240aaa2b766ac0d8a2045d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64464
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-03 20:06:01 +00:00
Patrick Georgi 7310789085 util/scripts/cross-repo-cherrypick: Modify output format
As far as I know the Chromium OS team is the only user of this script,
so align its output with that of other tools used there:

- Replace "Original-Commit-Id" with "GitOrigin-RevId"
- Reuse Change-Id instead of moving it to the Original- prefix, which
  leads to the creation of a new Change ID.

Change-Id: I8c39c512901c83a64f00aa48a539e6621f827242
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-03 18:44:51 +00:00
Martin Roth 8da4bfe5b5 util/release/build-release: Use short git hash for .coreboot-version
Builds were suddenly failing when the release was done, because the
coreboot version was overflowing a 64 character limit.  We don't need
or use the full hash in other places, so limit the hash to just what's
needed to identify the commit.

Change-Id: I57c535ca251792cae2c9a9c951e6b44bb61e4e78
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-06-03 03:10:05 +00:00
Julius Werner af20fd748b cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verification
The Intel Firmware Interface Table (FIT) is a bit of an annoying outlier
among CBFS files because it gets manipulated by a separate utility
(ifittool) after cbfstool has already added it to the image. This will
break file hashes created for CBFS verification.

This is not actually a problem when booting, since coreboot never
actually loads the FIT from CBFS -- instead, it's only in the image for
use by platform-specific mechanisms that run before coreboot's
bootblock. But having an invalid file hash in the CBFS image is
confusing when you want to verify that the image is correctly built for
verification.

This patch adds a new CBFS file type "intel_fit" which is only used for
the intel_fit (and intel_fit_ts, if applicable) file containing the FIT.
cbfstool will avoid generating and verifying file hashes for this type,
like it already does for the "bootblock" and "cbfs header" types. (Note
that this means that any attempt to use the CBFS API to actually access
this file from coreboot will result in a verification error when CBFS
verification is enabled.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01 19:45:22 +00:00
Julius Werner 0057262b38 cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOAD
There are too many "FIT" in firmware land. In order to reduce possible
confusion of CBFS_TYPE_FIT with the Intel Firmware Interface Table, this
patch renames it to CBFS_TYPE_FIT_PAYLOAD (including the cbfstool
argument, so calling scripts will now need to replace `-t fit` with `-t
fit_payload`).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I826cefce54ade06c6612c8a7bb53e02092e7b11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-01 19:45:08 +00:00
Martin Roth b3f91b7941 util/docker: Update dockerfiles
- Remove deprecated "MAINTAINER" lines
- Add Sphinx tools to coreboot-jenkins-node to check documentation.
- Add mdl to check markdown
- Alphabetize packages in docs Dockerfile
- Add jinja2 version 3.0.3 to the docs Dockerfile - The latest version
breaks with the error:
"exception: cannot import name 'contextfunction' from 'jinja2'"

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia1de62621a6aef4ecd055a1a3afbebad34448002
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-31 13:41:56 +00:00
Martin Roth 74129e5141 util: Update description files
- Spelling fix
- Add languages
- Update formatting
- Move notes that shouldn't be in the description file to a README

Change-Id: I4af37327d5834f8546a3f967585658fb5686f17a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-30 13:05:21 +00:00
Martin Roth e44a3d2842 util: Fix a few spelling mistakes
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6f0232292c9e289ee1e87998493ea70beea8e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30 04:25:07 +00:00
Martin Roth 81e0d689c0 Documentation: Move intelp2m from description.md to Documention
The description.md file for the intelp2m utility wasn't the description
that was needed - just a subject, and what language it was written in.
It was instead a set of more full documentation, so move it into the
Documentation directory and create a new description file.

Change-Id: Ia180ae41f91f8b8eb408351a9e44e899edc031d3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30 04:19:39 +00:00
Elyes Haouas 709fdb1995 util/lint/checkpatch: Add alloc functions to alloc with multiplies check
This reduce difference with linux v5.18.

Change-Id: Id9412f7b6c0b9f76b39a094142aaded5c2aa1059
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:38 +00:00
Elyes Haouas 069dfe33a3 util/lint/checkpatch: Update 'Check for compiler attributes'
This reduce difference with linux v5.18.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I817630321587dec515cd94aa7b73a17819526190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:21 +00:00
Elyes Haouas a7b0d38964 util/lint/checkpatch.pl: Use 'allocFunctions'
This reduce difference with linux v5.18.

Change-Id: I1fc71b9cb6a4e4f8b27fbe6d45f4fa4e2c236157
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:02 +00:00
Michał Kopeć 2d8edebc97 util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.

PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362).

TEST=dump GPIOs on i5-12600K with Z690 chipset

Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-05-28 14:36:50 +00:00
Arthur Heymans c2eb9e6e81 abuild: Build with clang only when supported
This changes the behavior of '-L/--clang' to only buildtest when a
target has ARCH_SUPPORTS_CLANG set.

Change-Id: I362fcd0f795d27f13dde793a79774f08c497bd38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28 05:23:21 +00:00
Martin Roth 97e7eea976 util/lint/checkpatch: Warn on period at the end of commit subject
This gives a warning when there's a period at the end of the commit
subject line.

Change-Id: If95bef3ba01e0ac13ce18045928081040abef4fd
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-28 01:26:03 +00:00
Martin Roth 341a53d1c5 util/lint: Subtract the patch format string from subject length
Checkpatch was looking for a 65 character length, but format-patch adds
the text "Subject: [PATCH] " before the actual subject.  Checkpatch
needs to account for that when looking at the line length.

Lines 2863 & 2864 have their indentation fixed as well.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f2ee6e0f1b14ae6393ed7e64ba1266aa9debc7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-28 01:25:48 +00:00
Martin Roth 9e33723d9b util/lint: Add commit message parsing to checkpatch_json script
The commit message wasn't being parsed because there's no filename
associated with it in the patch output.  This change adds the "filename"
for the commit message in Gerrit for any errors that have a line number
but no filename.

calculations is intentionally misspelled as cacluations as a test.

Change-Id: Ie7a2ef06419c7090c8e44b3b734b1edf966597cc
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-28 01:25:37 +00:00
Michał Kopeć d3b550d47c util/intelp2m: Add support for Alder Lake macro generation
Add support for Alder Lake as a separate parsing profile, copying the
existing 'Cannon' profile and adjusting for differences in reset mapping
and GPIO macro generation.

TEST=Generate GPIO macros for MSI PRO Z690-A

Change-Id: I5871394bcb0636c2c803607ffb129441aa934417
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2022-05-25 23:25:25 +00:00
Elyes Haouas 26e0b94614 util/lint/checkpatch.pl: Reduce difference with linux v5.18
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id5eb4823399088746a34721a9855bbaf5f97b7b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-24 12:57:48 +00:00
Maximilian Brune 94223c4165 Allow trailing whitespaces in .md files
Two trailing whitesspaces have an actual meaning in Markdown files (a new line).

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 19:58:31 +00:00
Robert Zieba 4098ecf5bd util/testing: Remove amdfwread from makefile
amdfwread was added to the testing makefile but ended up not becoming a
separate tool. This commit removes it from the makefile so that `make
distclean` works again.

Fixes: 29bc79fddb ("util/amdfwtool: Add
amdfwread utility")

TEST=Ran `make distclean`

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I2c8b920bc69d6c20558a28515c52a1e9cecebe27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 15:56:50 +00:00
Sean Rhodes 645dde7794 util/inteltool: Add support for Gemini Lake
Tested on:
* StarLite Mk III (N5000)
* StarLite Mk IV (N5030)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 07:04:22 +00:00
Martin Roth af06e9adea util/lint/lint-stable-019: Update grep '\s' to [[:blank:]]
For some reason, the '\s' syntax is causing an error for me under
freebsd.  It's entirely possible that I'm doing something wrong, but
this change should be fine regardless.

Freebsd's grep, GNU grep, and git grep all handle posix regex classes,
so this change should be transparent.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I489ec13b4ea2e9c17692888e42b8741763b1a2c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16 05:18:09 +00:00
Elyes Haouas 14c49e3646 util/lint/checkpatch.pl: Fix "uninitialized value" error message
Change-Id: I74807f240779060158c6769f63a6e9438a6e5fbe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:28:44 +00:00
Elyes Haouas 0014bce46b util/lint/checkpatch.pl: Fix "Invalid color mode" error message
Remove duplicated code:
"if ($color =~ /^[01]$/) {
	$color = !$color;
} elsif ($color =~ /^always$/i) {
	$color = 1;
} elsif ($color =~ /^never$/i) {
	$color = 0;
} elsif ($color =~ /^auto$/i) {
	$color = (-t STDOUT);
} else {
	die "$P: Invalid color mode: $color\n";
}"

Change-Id: I5713c364edea806e58df26c3a37b4bba7603ed0a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:28:02 +00:00
Robert Zieba 29bc79fddb util/amdfwtool: Add amdfwread utility
Amdfwtool creates AMD firmware images however there is currently no way
to get information from an existing image. This commit adds amdfwread to
support that functionality. At the moment only reading PSP soft fuse
flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`,
example output: `Soft-fuse:0x400000030000041`.

BUG=b:202397678
TEST=Ran amdfwread and verified that it correctly reads the soft fuse
bits, verified that built AMD FW still boots on DUT

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-13 15:51:37 +00:00
Arthur Heymans a0595759f6 xcompile,clang: increase the number of bracket-depth for CPP
Clang has a limit for the number of nested brackets in CPP.
For soc/intel/common/block/include/intelblocks this is a problem as it
largely exceeds the default limit of 256.

Change-Id: I93038f918e07f735394fc495a8ed7371cc5b1569
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13 11:03:16 +00:00
Karthikeyan Ramasubramanian 0ab04d2851 util/amdfwtool: Add IKEK key for Trusted Application
This binary file is required for use by Trusted Applications that
execute in PSP.

BUG=b:229947314
TEST=Build and boot to OS in Skyrim.

Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-05 14:48:31 +00:00
Yu-Ping Wu f1a8dde147 cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION
MediaTek's bootROM expects a SHA256 of the bootblock data at the end of
bootblock.bin (see util/mtkheader/gen-bl-img.py). To support CBFS
verification (CONFIG_CBFS_VERIFICATION) on MediaTek platforms, we need
to re-generate the hash whenever a file is added to or removed from
CBFS.

BUG=b:229670703
TEST=sudo emerge coreboot-utils
TEST=emerge-corsola coreboot chromeos-bootimage
TEST=Kingler booted with CONFIG_CBFS_VERIFICATION=y

Change-Id: Iaf5900df605899af699b25266e87b5d557c4e830
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63925
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-05 14:18:38 +00:00
Martin Roth 3201e1e68c util/scripts: Add options to update_submodules
This extends and adds various options to the update_submodules script.

Extensions:
- Add help text
- Add all options, but specifically allow a single repo to be specified,
along with a minimum number of changes instead of being fixed at 10.
- Make it a more formal script with main() and functions
- Show changes in commit message, unless there are > 65 commits.

Options:
-c | --changes <#>     Specify the minimum number of changes to update a repo
-h | --help            Print usage and exit
-R | --repo <dir>      Specify a single repo directory to update
-s | --skipsync        Assume that repos are already synced
-V | --version         Print the version and exit

This does not fix style issues in the original, which will be fixed in
a follow-on commit.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I222103babff7d5f4f8eb02869c598a4e06748a17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-04 13:12:23 +00:00
Manoj Gupta dfb8d80c1a utils/cbfstool: Disable Wstrict-prototypes warning
As recommended on crrev.com/c/3612466 lz4 code is not supposed
to be modified. Since both gcc and clang complain about
functions without explicit void in argument with Wstrict-prototypes,
just disable it instead instead of enabling.

BUG=b:230345382
TEST=llvm tot test
BRANCH=none

Signed-off-by: Manoj Gupta <manojgupta@google.com>
Change-Id: I9f3ae01821447f43b4082598dd618d9f8325dca2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63936
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-02 21:02:57 +00:00
Nick Vaccaro 946e29258c util/cbmem: fix an unused parameter issue in timestamp_get
Fix an unused parameter error when building on devices where __i386__
and __x86_64__ are not defined.

BUG=none
TEST=none

Change-Id: I6c04c8e7b931565c87d358aac1025ebcb7617b13
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63880
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27 00:32:29 +00:00
Zheng Bao 993b43f2be amdfwtool: Use command line option use-combo to decide if use combo
The macro PSP_COMBO is removed and instead use the flag use_combo. As
long as this flag is false, the amdfwtool behaves the same way as the
macro does.

Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25 14:48:16 +00:00
Zheng Bao 96a3371a72 amdfwtool: Change the name of macros for 'BHD'
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it
clear it is for level 2. The 'BHD2' is misleading, which is going to
be used for combo entry. The definition in psp_verstage is also changed.

Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-25 14:46:12 +00:00
Arthur Heymans 597b9e9d71 cpu/x86/64bit: Generate static page tables from an assembly file
This removes the need for a tool to generate simple identity pages.
Future patches will link this page table directly into the stages on
some platforms so having an assembly file makes a lot of sense.

This also optimizes the size of the page of each 4K page by placing
the PDPE_table below the PDE.

Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-25 14:00:41 +00:00
Elyes Haouas 43529c8b20 util/lint/checkpatch.pl: Update lines related to CONST_STRUCT
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0fe2ec6a74a4b8c70452fbf05d534a37e1ea2c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:19:40 +00:00
Elyes Haouas f0e150c35a util/lint/checkpatch.pl: Add strlcpy check
Update to v5.18-2

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ic4eaa3f26bcd60ea509a52d5715c7ce1f43b6d3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:18:55 +00:00
Elyes Haouas 8f59960fb2 util/lint/checkpatch.pl: Update C99_COMMENT_TOLERANCE lines
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If230fa5cd01ab3ce91d8c910667c3d609cf978b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:18:11 +00:00
Elyes Haouas 00d8ffdada util/lint/checkpatch.pl: Update TYPECAST_INT_CONSTANT lines
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I8ed89e53f647b1b071abff33a434fb3b8dbb1de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:17:34 +00:00
Elyes Haouas 84083a27aa util/lint/checkpatch.pl: Update the check of repeated words
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7f5e597bb76e1b9feeb2d6ea290626f45e9fe6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:17:00 +00:00
Elyes Haouas f62a98939d lint/checkpatch.pl: Update to v5.18-2 lines related to "CONFIG_"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I8589d053871ad9ac64ae2f8fc380710be8e4556b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:16:14 +00:00
Elyes Haouas 0b1a03cd18 util/lint/checkpatch.pl: Update lines related to max_line_length
Upadate to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib9927bfa98e20d4b621bf7abecec234b4754ee9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:16:04 +00:00
Elyes Haouas 41d43f5eeb util/lint/checkpatch.pl: Update lines related to tabsize
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:15:33 +00:00
Elyes Haouas 46b07e53f5 util/lint/checkpatch.pl: Update to v5.18-2 lines related to verbosity
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I66f38cb01e58ee241bf58c4db83693029ddebcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:14:24 +00:00
Mattias Nissler ecc165b789 util/cbmem: add an option to append timestamp
Add an option to the cbmem utility that can be used to append an entry
to the cbmem timestamp table from userspace. This is useful for
bookkeeping of post-coreboot timing information while still being able
to use cbmem-based tooling for processing the generated data.

BUG=b:217638034
BRANCH=none
TEST=Manual: cbmem -a 1234 to append timestamp, verify that cbmem -t
shows the added timestamp.

Change-Id: Ic99e5a11d8cc3f9fffae8eaf2787652105cf4842
Signed-off-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-22 22:43:36 +00:00
Jianjun Wang b2537bdad5 coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t
lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no
longer needed.

Also replace 'struct cbuint64' with 'cb_uint64_t' and remove
'cb_unpack64' in libpayload for compatible with lb_uint64_t.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-14 22:27:50 +00:00
Karthikeyan Ramasubramanian 4bdc2320a4 util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magic
APCB edit tool edits APCBs with LP4 specific SPDs. Introduce an option
to support different SPD magic so that the tool can be used to edit
APCBs with LP5 specific SPDs.

BUG=None
TEST=Build Skyrim board with LP5 specific SPDs. Build Guybrush board
with LP4 specific SPDs.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8e96c89e4e5ce8e0567a17bf7685b69080fa1708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63598
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14 22:24:09 +00:00
Karthikeyan Ramasubramanian 58d75f80b4 util/spd_tools/part_id_gen: Support Sabrina SoC
Add support to generate DRAM part ID for boards using Sabrina SoC.

BUG=None
TEST=Generate DRAM part ID for Skyrim mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ica57b12239019831f7bf93982be3c93b7f8b6986
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14 22:23:51 +00:00
Karthikeyan Ramasubramanian ad06bae7b1 util/amdfwtool: Maintain one copy of PSP Level2 entries
AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot
A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which
use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2
entries in each FW slot is redundant and space-consuming. Introduce
option to maintain only one copy of PSP Level2 entries and point to it
from both slots A & B.

BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added
to each FW slot. This achieved a space saving of 1.5 MB in each FW slot.
Before:
apu/amdfw                      0x415fc0   raw           3043328 none
After:
apu/amdfw                      0x415fc0   raw           1556480 none

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-14 15:39:15 +00:00
Zheng Bao c3007f3877 amdfwtool: Add a flag to record the second gen instead of romsig
This is for future feature combo, which gets the soc id from fw.cfg in
a loop instead of the command line, and the romsig is not set until
fw.cfg is processed.

Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-13 23:25:00 +00:00
Elyes Haouas 84ef4fb15b util/lint/checkpatch.pl: Update to v5.18-2 lines related to "codespell"
Change-Id: I55cc4255ea88723c813a04d87e4c028c64f92dbd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-04-11 13:59:59 +00:00
Michał Kopeć bd656b4e4c superiotool/ite: add IT8625E EC registers
Add support for dumping ITE IT8625E Environmental Controller registers.

Values as per "IT8625E Preliminary Specification V0.3 (For D Version)".

Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-06 16:28:53 +00:00
Zheng Bao 487d04540b amdfwtool: Add a macro to set explicitly second gen for old SOCs
It is more reasonable than getting the value from memset.

For the reserved bits, keep them as they were for old SOCs.

Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-05 17:45:58 +00:00
Robert Zieba 255b1fb38b util/spd_tools: Add ability to override SPD file for parts
This commit adds the ability to override the SPD file that is used for a
specific part.

BUG=b:224884904
TEST=Verified that generated makefile uses specified SPD file and that
it remains unchanged when this capability is not used

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05 14:50:56 +00:00
Elyes Haouas 9a8d0a03db crossgcc: Upgrade IASL from 20211217 to 20220331
"REDUNDANT_OFFSET_REMARK" to ignore redundant offset remarks is
not needed any more as it’s included upstream.

Changes: https://acpica.org/node/199

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-04 13:54:49 +00:00
Elyes Haouas 6d976919d0 crossgcc: Upgrade CMake from 3.22.2 to 3.23.0
Release Notes:
  https://cmake.org/cmake/help/v3.23/release/3.23.html

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib31124baa3cae65211ad361a7d41c9504105be91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-04 13:54:20 +00:00
Felix Held 11b0d360ba util/amdfwtool/data_parse: fix SPL table handling regression
Use the SPL table binary from the config file if no override is
specified via the spl-table command line argument. This fixes a
regression caused by commit 6c5ec8e31c
(amdfwtool: Add options to support mainboard specific SPL table).

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-03 17:06:48 +00:00
Paul Fagerburg ac68384c0c util/cbmem: add type cast
arch_convert_raw_ts_entry returns a uint64_t, which needs to be cast
on ARM systems to avoid a type error.

BUG=b/227871959
TEST=no build errors in downstream

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I87a83758b7f122b77f9631c669c7cd8df66f8d1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63317
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02 16:12:28 +00:00
Arthur Heymans 8b82c6b91b util/ifittool: Fix clearing FIT when setting the pointer
When setting the FIT pointer, the FIT table is only known later in the
codeflow.

Change-Id: I658f4fffa997d1f7beaf6d6ae37d2885ae602e5c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63035
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 09:29:19 +00:00
Jakub Czapiga 48f6c2b46f util/cbmem: Add FlameGraph-compatible timestamps output
Flame graphs are used to visualize hierarchical data, like call stacks.
Timestamps collected by coreboot can be processed to resemble
profiler-like output, and thus can be feed to flame graph generation
tools.

Generating flame graph using https://github.com/brendangregg/FlameGraph:
  cbmem -S > trace.txt
  FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg

TEST=Run on coreboot-enabled device and extract timestamps using
     -t/-T/-S options

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-31 23:04:58 +00:00
Felix Held f8e2e47e2b util/amdfwtool: use ISH support for Sabrina SoC
The PSP in the Sabrina SoC uses the image slot header to find the second
level PSP directory table, so it needs the ISH to be generated.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9e6308854147c9f6f72d722215c833ee86ee4f94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63186
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:42:14 +00:00
Felix Held b18a4c7d0d util/amdfwtool: add Sabrina SoC type
Add PLATFORM_SABRINA to the enum of supported platforms and integrate it
into the existing code.

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe52b44395619f697686bd900a522562abbe7646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 23:41:53 +00:00
Felix Held 830add6e27 util/amdfwtool: select A/B recovery when ISH is used
In newer AMD SoCs, the image slot header is used in the AMD A/B recovery
scheme, so set recovery_ab to true when need_ish is true. Also move the
block of code before the process_config call, since that call will
already use the recovery_ab field of the cb_config struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:41:48 +00:00
Felix Held 21a8e381ea util/amdfwtool: use table-relative addressing in ISH case
When the image slot header (ISH) is used, the addresses in the PSP and
BIOS directory tables need to be relative to the beginning of the table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 22:20:04 +00:00
Idwer Vollering 70f3d43854 util/genbuild_h: micro-adjust the regexp used to set COREBOOT_MAJOR_VERSION
On FreeBSD, every build target would show warnings from its
builtin printf().
Change the regexp to be compatible with BSD sed.
This will avoid noise like "printf: 4.14-1278-g5d74ccf1c3: not
completely converted".

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: I1c0c260fd8d42e23a612a353a288e472cc068c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-03-30 20:06:57 +00:00
Zheng Bao 3a6ab474e0 amdfwtool: Clear the whole byte of EFS_GEN
Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-29 15:41:20 +00:00
Zheng Bao fdd47ef1e6 amdfwtool: Add ISH header support for A/B recovery layout
Image Slot Header (ISH) is a new feature.
The rom layout for A/B recovery with ISH:
EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A
              0x4A -> ISH B -> PSP L2 B -> BIOS L2 B

The newer 55758 will updated about the boot priority and update retry
in ISH header.

Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27 15:24:15 +00:00
Felix Held 5f18bb75fb util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types
Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware
table entries, so add those as a preparation for Sabrina support.

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-27 15:21:21 +00:00
Martin Roth 10d34b7818 util/lint/checkpatch: Update commit message & subject line limits
The commit message has a (soft) line length limit of 72 characters and
the subject has a (soft) line limit of 65 characters. This change
updates checkpatch to warn at those limits.

Note that neither of these are hard limits because git & gerrit can both
handle longer lines, it just doesn't look good.

Change-Id: I4ef131a65254e2b184b05e0215969aef97e12712
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-25 19:23:59 +00:00
Zheng Bao fb9b784ca2 amdfwtool: Change the some FW's level for A/B recovery
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.

The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.

Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-23 20:17:45 +00:00
Robert Zieba a6425f170c util/spd_tools: Add support for exclusive IDs
Currently memory parts that use the same SPD are assigned the same ID by
spd_tools. This commit adds support for exclusive IDs. When given an
exclusive ID a memory part will not share its ID with other parts unless
they also have the same exclusive ID.

BUG=b:225161910
TEST=Ran part_id_gen and checked that exclusive IDs work correctly and
that the current behavior still works in their abscence.

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-22 16:17:06 +00:00
Bora Guvendik c79da5f211 util/cbmem: Keep original Total Time calculation when no negative timestamps
"Total time" calculation changed after CL 59555 to include
"1st timestamp" value in the calculation. This patch restores original
Total Time calculation where "1st timetamp" is subtracted from
"jumping to kernel". If pre CPU reset timestamps are added (negative
timestamps), "Total time" calculation still includes the pre-reset time
as expected.

1) Before https://review.coreboot.org/c/coreboot/+/59555:
   0:1st timestamp                                     225,897
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,012,281

2) After https://review.coreboot.org/c/coreboot/+/59555:
   0:1st timestamp                                     225,897
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,238,178

3) After this patch:
   0:1st timestamp                                     225,897 (0)
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,012,281

BUG=none
TEST=Boot to OS, check cbmem -t on Redrix board

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-21 20:30:05 +00:00
Zheng Bao 52a1898d44 amdfwtool: Check the length of matching string before accessing
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.

Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-21 16:55:46 +00:00
Felix Singer 9bd35ddb35 util/liveiso: Remove coreboot toolchain from todo
The coreboot toolchain is a huge blob and increases the size of the
build a lot. If needed, the specific toolchain can be added before
building the ISO or with `nix-shell` later in the live system, as shown
below.

  $ nix-shell -p coreboot-toolchain.i386

Thus, remove this from the todo list.

Change-Id: Ia24ceb84f202828f1c97d3ba5bafbf6af0361bdb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-17 18:51:35 +00:00
Subrata Banik ca82e6161a util/ifdtool: Add Meteor Lake platform support under IFDv2
BUG=b:224325352
TEST=Able to build ifdtool.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3564efa27d0271286435284e745458aada987008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-15 19:22:49 +00:00
Julius Werner ce87832c66 cbmem: Fix console banner matches
Since the new loglevel markers were added, there will now be a marker
character at the beginning of the coreboot banner string, and this will
make the existing regular expressions meant to find it fail to match.
This patch fixes the problem by just allowing for a single extra
character there (any character to avoid the hassle of having to match
the marker explicitly). The extra character is optional so that we will
still continue to match banners from older versions of coreboot as well.

Since the `?` glyph is not available in basic POSIX regular expressions,
we have to switch to REG_EXTENDED syntax (should otherwise make no
difference). (Also, move side effects out of assert() while I'm here,
that's not actually safe for the standard libc implementation.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62720
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 23:42:53 +00:00
Martin Roth d5f45d0a9e util/futility: Don't echo the warning message unless it fails
Currently, all of the commands for building futility are printed as they
are run.  This change skips printing the check for libcrypto unless the
check actually fails.  This prevents the error from being displayed when
there isn't actually a problem.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9ef36c0b64f7cd69d19b8faabd165ef6651c838e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 16:16:55 +00:00
Arthur Heymans efdcb4634a cbfstool/linux_trampoline: Fill the ACPI RSDP entry
With LinuxBoot Linux relied on the legacy method of fetching the RSDP
pointer to get ACPI. This uses a more modern approach available since
2018 on the Linux kernel, which involves filling in the zero page.

This method takes precedence over any other method of fetching the
RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are
threatening that legacy code will be removed from Linux so it's best
to already adapt to that possibility.

Tested on Qemu:
- With qemu the RSDP is always in the EBDA, so checking if Linux uses
  the provided pointer is better done with a forced bad entry
- With a fake bad pointer Linux correctly does not find RDSP

Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09 14:21:26 +00:00
Zheng Bao 4df5af87be amdfwtool: Clear struct match before regular expression matching
If it is not cleared and the number of strings is fewer than last
iteration, the match[3] will keep the last value, which actually
should be empty.

Add assert to make sure the level is a legal value.

BUG=b:222038278

Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-09 14:02:21 +00:00
Julius Werner 69cc557cfb commonlib/bsd: Remove cb_err_t
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 02:18:21 +00:00
Karthikeyan Ramasubramanian f53214677c util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle
time. Encode tCKMin as per the respective advisories.

BUG=None
TEST=Generate the SPD and ensure that tCKMin is encoded accordingly.
Minimum CAS Latency time is also impacted and is encoded accordingly.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-08 23:46:50 +00:00
Jeff Daly abd4b96eb4 util/ifdtool: Add support for Denverton SoC
Denverton is a special version of IFD2 flash layout.  It defines
10GbE firmware regions (11/12) and the IE (10) region which
other IFD2 platforms do not have.  Denverton does not include the
legacy GbE region (3) or the EC region (8) which other IFD2
platforms do have.

TEST='ifdtool -p dnv coreboot.rom' and verify correct output

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08 15:03:39 +00:00
Martin Roth 1fcf78cc8e util/docker/coreboot-jenkins-node: Alphabetize installed tools
It's easier to read and to add new packages when each package is on its
own line and they're sorted alphabetically.

Indenting them also makes it easier to see what's getting installed and
what's a command.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62446
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 13:09:55 +00:00
Martin Roth c8a1195b77 util/docker/coreboot-jenkins-node: add linkchecker
The linkchecker tool is now being used to find broken links in our
websites.  Since it's not needed for building anything, just add it to
the jenkins-node Dockerfile instead.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iac2246b5378e556b5cd9f2107fc5a7e51d583b5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62445
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 13:09:40 +00:00
Felix Singer 2060bff9c0 utils/cbfstool: Fix building with `make test-tools`
The variable `RM` is empty and thus set it to `rm`. While
executing the `clean` rule, run each `rm` command with the -f flag
to ignore non-existing files.

Also, disable the objutil feature locally fixing another build issue.

Change-Id: Icb17e2c924ef480f8ac6195f96cf495709a0a023
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62415
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-27 18:29:24 +00:00
Martin Roth e61e7789c2 util/testing: Add cbfstool tools to tested utils
Previously, cbfstool was tested as part of the coreboot build, but not
tested individually. This let a change that broke elogtool slip through.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9e7b7a01d4a77ffdac932ba5af12cbd1ba96628b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-27 02:21:23 +00:00
Martin Roth e3e965b13d Revert "util/cbfstool: Port elogtool to libflashrom"
This reverts commit d74b8d9c99.

This change breaks the 'make all' build of the cbfstool tools
from the util/cbfstool directory unless libflashrom-dev is
installed, complaining that flashrom is not installed.

Even with libflashrom-dev installed, it breaks building
elogtool with the public version of libflashrom-dev.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I572daa0c0f3998e20a8ed76df21228fdbb384baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62404
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 01:24:17 +00:00
Elyes HAOUAS a0b8032279 crossgcc: Upgrade LLVM/clang from 12.0.0 to 13.0.1
Build/run not tested on board.

Change-Id: I8c550d3528a5b1c891b318c08ecfba3a9255e69c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59400
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:10 +00:00
Zheng Bao fdb0294846 amdfwtool: Check the real length of PMU string
The length should be checked before the PMU_STR_INS_INDEX(th) character
is accessed, otherwise it is going to an access violation.

Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-24 00:41:45 +00:00
Felix Singer 88ccd4863c util/nixshell: Add a Nix shell for building documentation
Add a Nix shell config allowing to build the coreboot documentation.

Change-Id: I1c9715c677342241b78fbdef0afeb4536f48d50f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-22 10:31:41 +00:00
Zheng Bao e220faa18a amdfwtool: Add entries for PMUI & PMUD with instance 2
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21 23:48:57 +00:00
Zheng Bao 990d154898 amdfwtool: Add support for AMD's BIOS A/B recovery feature
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
              0x4A -> PSP L2 B -> BIOS L2 B

The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.

To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.

TEST=Majolica(Cezanne)

Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 23:47:20 +00:00
Zheng Bao 1a9e54302b soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.

Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 21:29:50 +00:00
Felix Singer 3a5e6f529c util/liveiso: Use programs.flashrom.enable
NixOS 21.11 introduced the option `programs.flashrom.enable`. The option
allows installing flashrom and hooking up its udev rules. Thus, set it
to `true` and add the user `user` to the `flashrom` group allowing it to
use the programmers.

Change-Id: I017ddb4314702a5252dfc0d05cd1e4961043d23b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-21 15:25:18 +00:00
Elyes HAOUAS e854b0b5e7 crossgcc: Upgrade CMake to 3.22.2 version
Change-Id: I4272f72dd6ed686dbad5615a0ab44c8c632b5930
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-21 08:05:48 +00:00
Karthikeyan Ramasubramanian e1d6f5b80d util/spd_tools/spd_gen/lp5: Encode Bank Architecture
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or
16B Bank Architectures depending on the speed. This influences SDRAM
Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the
individual SoC advisories.

BUG=b:211510456
TEST=Generate SPDs for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17 21:43:29 +00:00