Commit Graph

7876 Commits

Author SHA1 Message Date
Ronald G. Minnich 1c706dc858 Fix the stack setup code so we can use an arbitrary 32-bit value
We've had obscure errors as the size of the bootblock changes.
This fix allows us to use a 32-bit constant. Please test on
real hardware before you ack.

Change-Id: Ic3d9f4763554bd6104ae9c4ce5bbacd17b40872c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2168
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-17 21:36:59 +01:00
David Hendricks e2851f2812 make main() in snow's romstage.c our romstage entry point
Our earlier attempt was jumping straight from asm to the old u-boot
board_init_f in lowlevel_init_c.c. We are getting ready to transition
to using a real bootblock for ARM, so add romstage.c to the files
compiled and we'll make main() our entry point.

This also updates romstage.ld to place main() (*(.text.startup)) at
the beginning of romstage.

Change-Id: Ifc77a6bfba27d915c4cad62c6c8040665294628a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2163
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17 02:24:58 +01:00
Stefan Reinauer 88c4939c1b make crossgcc: compile all required toolchains
The ARMv7 toolchain is now also needed for abuild (at least
if you want to be able to compile ARM images)

Change-Id: If1253203a2198f7dea632ba45540222ba3361932
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2147
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-17 01:56:53 +01:00
David Hendricks 018724ec1b remove argument in snow's romstage main()
We don't pass any arguments into romstage on ARM.

Change-Id: I018f28a57fc486c9240345cf0f4043b79027d864
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2162
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17 01:53:34 +01:00
David Hendricks 694719aff0 bootblock_cpu_init() stub for exynos5250
This adds a stub for bootblock_cpu_init() for exynos5250. It will
eventually contain code to copy ROM content from SPI to SRAM.

Change-Id: I26ee62a1e701013f38f76f200579faa680530860
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2138
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17 01:07:40 +01:00
David Hendricks 0b23d47ffd armv7: Place reset vector + CBFS header + bootblock dynamically
This replaces hard-coded bootblock offsets using the new scheme.
The assembler will place the initial branch instruction after BL1,
skip 2 aligned chunks, and place the remaining bootblock code after.

It will also leave an anchor string, currently 0xdeadbeef which
cbfstool will find. Once found, cbfstool will place the master CBFS
header at the next aligned offset.

Here is how it looks:

             0x0000 |--------------|
                    |     BL1      |
             0x2000 |--------------|
                    |    branch    |
    0x2000 + align  |--------------|
                    |  CBFS header |
0x2000 + align * 2  |--------------|
                    |   bootblock  |
                    |--------------|

TODO: The option for alignment passed into cbfstool has always been
64. Can we set it to 16 instead?

Change-Id: Icbe817cbd8a37f11990aaf060aab77d2dc113cb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2148
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17 01:06:43 +01:00
David Hendricks 3d7344a7a1 ARM bootblock approach
This lays out the groundwork for using a proper bootblock on ARM.
Currently we bypass the bootblock entirely and go straight to
romstage. However we want to utilize CBFS to maximize flexibility
of placing code without relying on a lot of magic numbers which
will break depending on the SoC in use.

Change-Id: I9cc2a8191d2db38b27b6363ba673e5a360de9684
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2118
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17 01:06:16 +01:00
Martin Roth 09574d5c3c Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS
Bits were being shifted off the end of the mask accidentally.
This results in all masks being 32 bits wide instead of 48.

Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2146
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-16 23:59:08 +01:00
David Hendricks a12eaccc0b use a relative path for #line 3
The current path doesn't make much sense (unless you're Sven)
and may also incur a very long access penalty if /home happens
to be on a network mounted filesystem.

Change-Id: I8cfceb3cf237757ce9ea8f1953bce5a72691838a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2153
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-16 09:58:00 +01:00
Stefan Reinauer 9382bd65d4 armv7: delete unneeded ptrace.h
... and delete traces in source files.

Change-Id: Ie0f70a479f1eadadc654a41fa3c426d1d4ac2f2b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2152
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-16 00:48:03 +01:00
Stefan Reinauer 09e16dc215 libpayload: Style fixes
Change-Id: Ic3164fbffd8da6bd9d506d80e425ad89efc0f1af
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/2144
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-01-15 09:29:30 +01:00
Stefan Reinauer 816e9d1f0e Support for Celeron 1007U
Change-Id: I6b96b0e387dc3e6985eb1476fea612772a2288bc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2145
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-01-14 23:21:03 +01:00
Ronald G. Minnich 850793f6d0 Make the pre-commit-hook happy about the code in libgcov.c
Make the comments match what pre-commit-hook wants.

Change-Id: Ib99a6583f97221df3638bd3b7723f51d5f9c223c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2143
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-14 03:48:20 +01:00
Stefan Reinauer d37ab454d4 Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.

See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.

To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.

For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/

Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12 19:09:55 +01:00
Stefan Reinauer 6e21f43008 No random directories
Please, don't just add random directories for a single file because
it seems convenient. There already is a chromeos directory, that should
be used.

Change-Id: I625292cac4cbffe31ff3e3d952b11cd82e4b151e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2137
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12 18:25:06 +01:00
Ronald G. Minnich 6a01563d06 Move init.S to a proper filename
Also, remove unnecessary junk and prepare for future build changes.

Change-Id: I143777ec7e67ea4d6fed00084aafcb94c7866b4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2141
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-12 00:28:01 +01:00
Stefan Reinauer 8d05322b68 Fix console.c with serial support disabled
During the ARM port, disabling serial console became broken.
This patch fixes it.

Change-Id: I40460596073918a08c19bb9c991cada341cca940
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2136
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11 20:03:30 +01:00
Stefan Reinauer b8ad224468 cbmem: replace pointer type by uint64_t
Since coreboot is compiled into 32bit code, and userspace
might be 32 or 64bit, putting a pointer into the coreboot
table is not viable. Instead, use a uint64_t, which is always
big enough for a pointer, even if we decide to move to a 64bit
coreboot at some point.

Change-Id: Ic974cdcbc9b95126dd1e07125f3e9dce104545f5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2135
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11 19:56:43 +01:00
David Hendricks ea22796eda armv7: Add temporary build script for CrOS devs
This build script will:
- Build coreboot.rom
- Download BL1, extract and place it if necessary
- Do a partial flash via Servo, using some flashrom trickery to
  make the process fast.

This probably should not be submitted, unless the intention is to
back it out eventually.

Credit goes to Hung-Te for writing the original version.

Change-Id: Ia7a4bea6077416fc06768a5de5ee07edc973ede2
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2134
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11 01:45:48 +01:00
David Hendricks eb5e252ce1 exynos5250: Hacked up lowlevel_init_c
This is the first lowlevel init routine that gets called in romstage.
It's fugly and needs a lot of clean-up, but does the job for now.

Change-Id: Id54bf4f1c3753bcbed5f6b5eeb4b48bc3b41ce93
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2133
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11 01:45:12 +01:00
David Hendricks b9fb213f85 exynos5250: Temporarily remove intermediate rule in Makefile
This cannot be used until we get the BL1 mess sorted out.

Change-Id: I2490addb31256e27caa89ebb5b1501296e6903bd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2132
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-11 01:06:32 +01:00
Zheng Bao 105da50df4 AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS
The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these
bits will cause exception. So be carefull when spread this change.

The supermicro/h8scm needs more work. Currently it is set as it was.
We need to check if the F10 and F15 have different value.

Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-11 00:42:07 +01:00
David Hendricks 8a5ee9ce04 armv7: replace magic constant for romstage location
This replaces 0x02023400 with an SoC-specific Kconfig variable.

Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2130
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 23:13:39 +01:00
David Hendricks d6b0889feb add a few entries to .gitignore
- Development friendly files (tags, clang_complete)
- Cross-compile stuff (xgcc, tarballs)

This patch was originally written by Stefan.

Change-Id: I4229414c94ee04a4f38a748369c4ac90fda57aea
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/2128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-10 22:51:20 +01:00
David Hendricks 1dcb697a24 armv7: add *(.data) back into .romdata section
This doesn't seem to be strictly required (so far), but makes sense.

Change-Id: I18416c427ff886507ae09c7fc1a018baf94af24a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2131
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 22:33:13 +01:00
David Hendricks c82ec0ed33 armv7: update board_init_f function signature
We don't pass arguments when we jump out of assembly code.

Change-Id: Iccf3a6f713e260b08f9ff47e8b542b9e96369166
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2122
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 20:27:08 +01:00
David Hendricks 9ad1f56951 armv7: dynamically calculate the branch offset in cbfstool
This tidies up the ARMV7 case when creating cbfs:
- Calculate the offset using the size of the master header and offsets
  rather than using a magic constant.
- Re-order some assignments so things happen in a logical order.

Change-Id: Id9cdbc3389c8bb504fa99436c9771936cc4c1c23
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2125
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 18:01:14 +01:00
David Hendricks 8bc10b74dc armv7: delete some unused files
Change-Id: I4601b97cbd7dbfb6ee742b3920d2aac4ac49b958
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2121
Tested-by: build bot (Jenkins)
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2013-01-10 12:18:51 +01:00
David Hendricks 4868a1179d snow: add max77686 driver in romstage and ramstage
Change-Id: Id3e20b1ab5d85cfd22e2dae2750f32007b7f8f74
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2123
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 05:57:06 +01:00
David Hendricks 5f6d857dea exynos5250: clean-ups for clock_init
This does some clean-up for the exynos5250 clock_init.c:
- No global data.
- Remove some unused #includes
- Hard-code the memory type for Elpida DRAM. This will need to be
  fixed eventually (or the system will be unstable), but is good
  enough for early bring-up and until we finish other re-factoring.

Change-Id: Icd2cf8ba35058cbd1131666db311dfb77ef1a160
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2127
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 05:56:30 +01:00
David Hendricks 27094b0afe exynos5250: un-comment a lot of code which was left out earlier
Turns out initializing power rails is necessary, even for getting
serial output.

Change-Id: I3042c1001ae43b1e793ee6cb90bb79b8db0f8fd1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2126
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 05:55:46 +01:00
David Hendricks 1d5390ecc8 size optimizations for max77686
This contains some size optimizations for the Maxim MAX77686 driver:
- change max77686_para.vol_{min,div} from u32 to u16 (currently their
  max value is 50000 so it should be fine)
- remove max77686_para.regnum which takes 4 bytes for each and is not
  used

(Patch was originally written by Hung-Te Lin, I'm just uploading it)

Change-Id: I24044427c49467e99380d1f60ebc59e69c285b22
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2124
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 05:54:53 +01:00
Martin Roth 92dd172a57 Fix 2 infinite loops if IMC doesn't respond
ACPI code:
The ACPI code is not currently being compiled in by default, but
assuming that it will be at some point, I'm fixing the loop that
waits for the IMC to respond after sending it a command.  The
loop now exits after 500ms, similar to the function in agesa.

Agesa Code:
a 16 bit variable will always be less than 100000.  Change to
be a 32 bit variable.

Change-Id: I9430ef900a22d056871b744f3b1511abdfea516e
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2119
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-10 02:04:18 +01:00
Martin Roth 238780c8da Fix typo in SB800 Kconfig for IMC position
The cimx/sb800 IMC Firmware location Kconfig option has
a typo which would could set it to the wrong location.

Change-Id: I38016bebd1bfe6ad6d3f1c02cb1960712fbf4ab2
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-09 20:52:47 +01:00
Stefan Reinauer 597ff87574 qemu-x86: Implement more features
This patch switches the Qemu target to use (pseudo) Cache As RAM
and enables some ACPI code. This allows to use the CBMEM console
and timestamp code with coreboot in Qemu. Right now, the ACPI code
is commented out because leaving it in breaks IDE.

Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2113
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08 23:33:35 +01:00
Stefan Reinauer c01990789f cbmem utility: Find actual CBMEM area
... without the need for a coreboot table entry for each of them.

Change-Id: I2917710fb9d00c4533d81331a362bf0c40a30353
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2117
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08 20:40:26 +01:00
Stefan Reinauer d7144dcd57 cbmem utility: unify debug output
... and indent it to make output more comprehensible.

Change-Id: If321f3233b31be14b2723175b781e5dd60dd72b6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2116
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08 20:25:21 +01:00
zbao 062730d7cb cbfstool: index is replaced by strchr.
From index(3):
CONFORMING TO 4.3BSD; marked as LEGACY in POSIX.1-2001. POSIX.1-2008
removes the specifications of index() and rindex(), recommending
strchr(3) and strrchr(3) instead.

Change-Id: I3899b9ca9196dbbf2d147a38dacd7e742a3873fe
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2112
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-08 04:00:30 +01:00
Stefan Reinauer 19f8756f00 cbmem utility: Add option to dump cbmem console
This adds an option to the cbmem utility to dump the cbmem console.
To keep the utility backwards compatible, specifying -c disables
printing of time stamps. To print both console and time stamps, run
the utility with -ct

Change-Id: Idd2dbf32c3c44f857c2f41e6c817c5ab13155d6f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2114
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2013-01-08 01:24:11 +01:00
Stefan Reinauer 1665bb3896 cbmem utility: drop obsolete python based implementation
The first version of the cbmem utility was written in python,
but it had issues with 64bit systems and other little hick ups.
Since the C version has much fewer dependencies (no python needed
on target system), and it works in all corner cases, drop the
python version.

Change-Id: Ida3d6c9bb46f6d826f45538e4ceaa4fc1e771ff5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2115
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-08 00:04:33 +01:00
Stefan Reinauer 2f25d9963e ARMv7: drop __ASSEMBLY__
We moved to using __ASSEMBLER__ years ago since it is set by as.

Change-Id: I60103ba23ebe87be1d0bc63beed0ef5b05eed4f2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2111
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-01-05 01:41:14 +01:00
Stefan Reinauer 9bcab0c72b Update 3rdparty mark to latest repository
Change-Id: I59fca4427345c7e677138b944613a1554d5a8331
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2110
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-01-05 01:31:12 +01:00
Stefan Reinauer 6d47cbe758 ARMv7: drop __KERNEL__
It's a bad Linux heritage.. We have no userland in firmware.

Change-Id: Ib19e5ba713078ca37514571213d19f418417b964
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2108
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-05 00:32:13 +01:00
Stefan Reinauer 9da7570b07 cbfstool: Fix warnings on OS X
Most hton and noth functions are already available
through the system headers we include on OS X, causing
the compiler to warn about duplicate definitions.

Change-Id: Id81852dfc028cf0c48155048c54d431436889c0e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2106
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-04 23:29:37 +01:00
Ronald G. Minnich 2485df3897 Flatten the tree
It makes no sense to have directories with one file.

Change-Id: I65ba93dda5e6a4bcc5a7cc049c1378ebf5d6abcd
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2105
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-04 23:24:15 +01:00
Ronald G. Minnich fa60de996d Revert "armv7: pass bootblock offset from Kconfig into cbfstool"
This reverts commit ec8d35fe91

We are almost certain that this is not necessary.

Change-Id: I70e94f883be95655da00a0b127ed9ffd7c81c63b
Reviewed-on: http://review.coreboot.org/2104
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-04 23:11:27 +01:00
Stefan Reinauer 853f4698a8 ARMv7: Make ABI compatible to reference toolchain
Our reference toolchain uses -mabi=aapcs whereas we started
forcing -mabi=aapcs-linux. Drop this to prevent ABI incompatibility.

Also drop -fno-common since that's set in the top level Makefile.inc
already.

Change-Id: I4afdcf5da9a5d86c2f9e5de5c7d523ccd2f5f1e0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2103
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04 22:14:19 +01:00
Stefan Reinauer 3a8badc265 ARMv7: drop libgcc copy
We accidently checked in some files from libgcc as well as
a Makefile from u-boot and a duplicate implementation of div0.

Drop all those files to reduce the confusion.

Change-Id: I8ff6eabbced6f663813f8cc55f19c81839d03477
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2102
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04 22:13:43 +01:00
Stefan Reinauer 31c36137f9 Clean up ARMv7 architecture Kconfig
There was a misuse of bool that would cause the dcache policy to not be
set up correctly, but instead present options "y" and "n" in the Kconfig
menu.

Also, TINY_BOOTBLOCK was removed a while ago, everything is
TINY_BOOTBLOCK now. Hence remove the option.

Change-Id: I5c28ac828955c69614c7bdaf106f79db51e68723
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2101
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04 19:35:25 +01:00
Stefan Reinauer c4077d4429 Make PCIe config options depend on PCIe support
Change-Id: I42452a044dc75e35876fcea1736481e538eed663
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2100
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04 19:35:14 +01:00