In function 'set_power_limits' there is a path to bail out early if the
Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS is selected. In this case
reading the MSR PLATFORM_INFO is useless and can be avoided. So read it
right before the value is needed.
This was found by the scanbuild.
In addition, fix an unnecessary line break to increase code readability.
Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO. I'm making this an error because we should really clean these up.
BUG=b:210694108
TEST=Boot guybrush and see error:
> I2C: 02:5d: ERROR: Exposing GPIOs in Power Resource and _CRS
> \_SB.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
When using site-local we need to have ability to override
MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in
site-local). site-local Makefiles.inc should be pulled in first
(different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten.
Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Use the common device ops instead of an soc-specific device ops.
TEST=builds for each soc
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the generic data_fabric_acpi_name function and device ops to common
code.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I12053389a12081ddd81912a647bb532b31062093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Make the data_fabric_acpi_name function more generic, in preparation to
move it to common.
TEST=build chausie, dump ACPI tables, and inspect DFD0 to DFD7
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Morgana/Glinda have a different register mapping for data fabric access,
although the registers themselves are mostly compatible. The register
layouts defined by each soc capture the differences and the common code
can use those.
Move the register offsets to soc headers and update the offsets for
morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254,
rev 1.51
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Now that the socs have defined the DF FICAA and MMIO Control registers,
update the common code to use them.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch enables the radio frequency interference mitigation for Rex.
BUG=b:248391777
TEST=Booted to OS on Rex board. Verified RFIM DSM is presented to kernel
through ACPI SSDT.
Change-Id: I22f9861452c2c222dd7a33bfeb02c63b026bf2f7
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The DDR RFIM is a frequency shifting RFI mitigation feature required by
the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer
to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable
once it is externally available. This change has backport changes from
commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to
drivers) and provides the CNVi RFIM support for Meteor Lake.
BUG=b:248391777
TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG
register at the offset 0x5A40 of Mchbar and verified the BIT0
(RFI_DISABLE bit) is 0.
Change-Id: I87110bc10b98a27a8f274680597b15a1df488824
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67789
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of having callbacks into serial console code to set up the
coreboot table have the coreboot table code call IP specific code to get
serial information. This makes it easier to reuse the information as the
return value can be used in a different context (e.g. when filling in a
FDT).
This also removes boilerplate code to set up lb_console entries by
setting entry based on the type in struct lb_uart.
Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* Add DPC related definitions which are defined in 7.9.14 of PCIe
6.0 spec.
* Add AER related definitions which are defined in 7.8.4 of PCIe
6.0 spec.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This reverts commit 3bc9fbb496.
The patch that added hob_enhancedwarningloglib.h was marked as private
after the Jenkins run, so I didn't see and submit it before submitting
the patch that gets reverted by this commit. Temporary revert this patch
to fix the coreboot tree until the issue with the missing patch is
sorted out.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If56609dd2d91a70fe7e99ce86e0341f2b3fee3d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69229
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 059902882c.
A dependency of the previous patch that added the get_ewl_hob function
used by this patch was missing, so this patch needs to be temporary
reverted to revert the patch that breaks the build due to the missing
dependency.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idb2fa27e75eede1648ddbf82c8bfbeeb2e9220a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69228
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Add an option on Atlas to enable IBECC (In Band Error Correction Code),
which is currently needed for endurance testing.
Test: start atlas mainboard with Linux. See in dmesg that
IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs
and see in dmesg that Linux handles it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add In Band Error Correction Code to Alderlake SOC's.
It's currently needed and tested for the Prodrive Atlas mainboard.
After enabling it in the UPD, FSP-M takes care of enabling IBECC.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68756
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of having the config option PAYLOADS_NONE inside the choice of
payloads, make that a separate choice that enables the payload menu.
If the no_payload option is selected, this hides the other options
and keeps them out of the saved config file and config.h
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I932c65630261a5b39809abf4dfbda5bf932c6684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may
contain several warnings/errors related to core, uncore and memory, etc.
mainboard can override it in its romstage.c for its own
Enhanced Warning Log check.
Change-Id: I6f542e71d20307397c398fd757d9408438f681ed
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69143
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The input-gating is an experimental feature (but unfortunately default
enabled) and would lead to crash on MT8188, so we have to disable it
in the firmware stage.
BUG=b:233720142
TEST=CPUfreq in kernel test pass.
Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69089
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When enabling cpufreq-hw driver, it is required for MCUPM to access
secure registers. Therefore, we enable side-band to allow MCUPM to
access the secure registers.
BUG=b:236331463
TEST=It works well after boot to login shell.
Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Some of the cbmem area names have gotten longer, and were making the
output of cbmem -l look bad, so expand the name area to 20 characters.
Instead of printing a blank area if the name isn't recognized, call it
unknown.
Change the method of printing the title to match the way the actual text
of the table is printed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Cut and paste error.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Iae6213ac99bc5c64fd5dcd681c7922eafa011fc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69165
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This reverts commit a8172c329f.
In the aforementioned patch, we allowed MCUPM to access secure
registers and set the domain to DOMAIN_2.
Additional attribute settings are also required when a hardware is
set to a specific domain. Otherwise, there would be violation between
hardware. Since MT8188 is in bring-up stage, we simply enable access
register permission for the DOMAIN_0 by default. So remove the wrong
setting for MCUPM, SCP and SSPM.
We will complete DEVAPC setting when the settings are confirmed.
Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69139
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change disables support for memory types not used by each of the
chips. This will in turn remove the files for those memory types from
the platform builds.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Don't call into disabled memory type code, it won't work.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently, we're building support for all memory types into every board,
and letting the linker remove anything that isn't needed. This is okay,
but it'd be nice to be able to build in just what's actually needed.
This change adds options to specify both what is used and what is not.
By doing it that way, the default values don't change, but platforms can
start removing support for memory types that are not needed. When all
platforms (SoCs, CPUs and/or Northbridge chips) specify what memory
types they support, the defaults on the options to use a particular
memory type can be set to no, and the options not to use a memory type
can be removed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Co-authored-by is commonly used for changes that have more than one
author. Add it to the list to make Jenkins happy.
Change-Id: I7f66824febe3be756c64ebf44c94bc653a66f1e1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
This reverts commit 1bb9786da3 ("cpu/x86/mp_init.c: Set a bogus
initial lapic_id"), since it breaks MP init on amd/mandolin:
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #3
[INFO ] Initializing CPU #1
[INFO ] Initializing CPU #2
[EMERG] CPU: missing CPU device structureCPU: vendor AMD device 810f81
[DEBUG] CPU: family 17, model 18, stepping 01
[DEBUG] microcode: patch id to apply = 0x08108109
[INFO ] microcode: being updated to patch id = 0x08108109 succeeded
[INFO ] CPU #1 initialized
[ERROR] MP record 3 timeout.
[INFO ] bsp_do_flight_plan done after 1206 msecs.
[ERROR] MP initialization failure.
[EMERG] mp_init_with_smm failed. Halting.
TEST=The board boots again with the revert applied
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic1cae88f7345f9ff79e8f6e574521095b57c8cb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69186
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Bail out of mp_init if this function fails.
Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69109
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This makes it easier to catch errors later if the ap_init code fails to
properly set things up.
Change-Id: I938faf042bfa4fe1fc39e78ab740c9b210bc105c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69108
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Add structs to define the data_fabric register bitfields, updated per
glinda ppr #57254, rev 1.51
Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add structs to define the data_fabric register bitfields, updated per
morgana ppr #57396, rev 1.52
Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add structs to define the data_fabric register bitfields.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I01dcea783542ecc0a761191907c1273016f854c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Werner Zeh