Add board connectors and headers descriptions to SMBIOS. Specify
type 1 and type 2 fields as in vendor firmware.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64050
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Boot Ubuntu 22.04, load nct6687 kernel module and use lm-sensors
to display information about sensors on the SIO EC.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I55445a94f0de3510324b12558c4343e819412ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original firmware ships with PTT enabled by default on poweron.
PTT takes priority over SPI/LPC TPM so enable the CRB interface
until coreboot implements a way to select the interface and adapt
the API to handle any TPM detection.
TEST=Boot the board and see PTT is detected by Windows and Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apply correct configuration of HD Audio.
TEST=Launch ubuntu 20.04 and launch a YouTube video, check if
microphone detects an input in the system sound settings.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6acc22aa58f6cc99df1d48d651122e74fe08ec02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63723
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the full PCIe root port configuration. Proper initialization of
the root ports depends on the correct GPIO programming including
virtual wires. Do not program the CLKREQ signals in coreboot to let FSP
detect and configure CLKREQ pads. Otherwise the CLKREQ pads are
reprogrammed by FSP despite having GpioOverride=1. The pads that
should not be touched by coreboot are left commented in the board GPIO
file. CLKREQ reprogramming caused undefined behavior when ASPM and
Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe
x4 slot (coreboot printed a lot of exceptions and simply halted).
TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots
populated and check if they are detected and functional in Linux.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation to CB:63514, make use of the variant concept and convert
the existing T440p mainboard into a variant.
Change-Id: I3c7e06607135ce0a62c158e296b51e5311234505
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Override tdp pl1 value to 30W in CPU MSR.
BUG=b:238268367
TEST=Boot to Chrome OS and check cpu log show "CPU PL1 = 30 Watts".
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibbd5ecc4b87ede5a62799020c741e5bff2952144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Hide the device so that Windows does not warn about a missing driver.
Tested on system76/lemp10:
- EC functionality remains functional on Linux 5.18.6 and Windows 10.
- Windows 10 does not report the device in Device Manager.
Change-Id: Iffcb873b85e077535d4de5806d01ba309f46c017
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64700
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes: 5315e96abf ("arch/x86/postcar: Use a separate stack for C execution")
Resolves:
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/
thread/TGIWAKZKELJRAEMKJNYRJ55MX2CXYNCV/
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/
thread/2JC3GNJSGXUD6DRVUY7O2O3W6OM3E2MY/
5315e96abf broke platforms using FSP-M to tear down CAR. It was pushing
the value at '_estack' into %esp rather than the address '_estack'.
Change-Id: Ie1fc70bd60fe3a2519ffb71625a35630fa732ff6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65716
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Based on comments on CL:65534, update the non-early GPIO table.
These are cases where Arbitrage wasn't able to find a useful
heuristic, or the memory straps, where Arbitrage sees them as NC in
the schematic.
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6e00892243cd6af99dc1921ee3fc712f6cbb58c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65710
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Customize brya baseboard early GPIO table to add mem straps for
ghost4adl, change I2C bus for TPM to pins H6/H7, and remove pins which
are not used on ghost4adl (E16, H13).
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I126a66fc5d24fbefec99abf87862c55b50c5e398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65534
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Boot MSI PRO Z690-A WIFI DDR4 with SP1, KBC and EC exposed
to OS via ACPI. Configure SP1, ACPI, KBC and EC devices via
devicetree.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia489a39956c1448c7f11845ecc9e1df83ccb25ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63927
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add VBT from vendor firmware v5.24 and configure display outputs in
devicetree.
TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the
connected display via HDMI or DisplayPort on rear panel.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs.
TEST=Include the microcode from vendor firmware and FSP blob from
Intel R&DC. Boot the platform and see ramstage is executing.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
On nissa, WLAN should be a wake source, so don't put it into D3cold
during suspend.
BUG=b:233325709
TEST=Wake-on-WLAN works on nereid
Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
CPUIDs and Engineering Samples decoding based on DOC #618427.
Keep MICROCODE_BLOB_UNDISCLOSED for PCH-N SKUs as microcode
blobs are still missing.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb1337e5cbf5b82fdaceb7eb4661d708a32ff0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65564
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.
BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iffbd08351d083d2b550f309994af931bceb257d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Configure the unused virtual CNVi BT GPIOs to NC since we
are using BT over USB mode for Nissa.
BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Id84823b9ad921ebd7ff773d6cce581563613745f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65669
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Disabling the Package C-state demotion feature for nissa baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=b:235005582
TEST=Boot and verify that S0ix issue is resolved.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I4d586b962c27b86ee75651dcd655bc0868504646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65664
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds the support to enable/disable package c-state demotion
feature from the devicetree based on mainboard requirement.
BUG=b:235005582
TEST=Build and boot to verify that the right value has been passed to
the FSP.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I9e254988bc3d20b9f9e42a605cc0ebd419ab49ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Aligning the "memory" ranges in devicetree is supposedly only needed on
very old arm32 kernels. So let's get rid of it.
Incidentally this fixes smaller than 1MB memory regions where the size
would end up being 0.
Change-Id: Ibbf5e331c79ed4ae3ed8dd37bf7a974d2412ce12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add 0x7d55 as another ID for Meteor Lake graphics controllers.
TEST=Boot with MTL silicon to check coreboot log for DID2
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Based on latest schematic to update the PCIE and USB setting.
BUG=b:237659398
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I97989b7a8d9104379ffb0b454d7248d49855f680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
DPTF Policy and temperature sensor values from thermal team.
BUG=b:237640264
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I43340bd1acfe6ec2036ea80339dbf896615a456a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65563
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The LabTop was renamed to StarBook since the release of the Mk V.
This change keeps the directory name more relevant, as there are
more boards using the name StarBook.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3513fb56c1adf663ed7bcdade2cc52cd8c0d6f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65640
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Enable SaGv support for Kinox
BUG=b:238153479
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id4646f1621a414a1ec4e272c826b0baea2bb4e19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This contains the following commits:
* d55c315 mb/starlabs: Remove padding from logo
* 6412d38 mb/starlabs/starbook/cml: Update EC from 1.03 to 1.07
* fb72ac5 mb/starlabs/starbook/tgl: Update EC from 1.00 to 1.03
* cda5eaa mb/starlabs: Rename labtop to starbook
* f16020a Revert "soc/mediatek/mt8186: Update SPM firmware to
pcm_suspend_v0215…
This also changes starlabs/labtop Kconfig to use the new paths for
the EC binaries from the above commits.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I83143118af422276ee335ad4ef9eca76f54a9fc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Modify ddi_ports_config based on schematic.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_3 = HDMI
BUG=b:237419696
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7c0458f0dbd4637b91af9e01664073e1f8a7a614
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch fixes the issue with INTC1056 invalid resource reported by
alderlake-pinctrl Linux driver on ADL-S platform. The driver also
includes GPIO Community 3 in the GPIO list compared to ADL-N which
was missing in GPIO ACPI device.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A DDR4 WIFI and check there is
no invalid resource error reported by alderlake-pinctrl
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I23da68c247de86438cc2eef2b5a5a9aa711c1d7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently the EC's MKBP interrupt line is programmed as dual-routed to
both SCI and IOAPIC. The brya EC will pulse the MKBP GPIO and also
send a host event when there is an MKBP event for host to service.
This causes an extra SCI to be generated, and the kernel will respond
to each MKBP event with an extra unnecessary host command. Changing
the pad configuration for the MKBP GPIO to APIC only fixes this issue.
BUG=b:236706977
BRANCH=firmware-brya-14505.B
TEST=excess GET_NEXT_EVENT host commands are gone from EC log
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic7dd596987f6d34c69d46674bdd07785235e2d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65480
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EEs have observed the ramp down delay on this signal in more detail
and 40 ms can still meet the sequencing requirements.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since the GPU will be left powered on, the kernel has the opportunity to
save context and this method to save the BARs is not required.
BUG=b:233959099, b:236289930
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19cf12426361a53e3672c1e05aa6d68d5dd6627c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Michał Żygowski