7 Commits

Author	SHA1	Message	Date
Patrick Rudolph	c4d56d668f	Documentation: Advertise support for OpenSBI ... Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>	2019-08-06 12:04:01 +00:00
Patrick Rudolph	c1b7e8a60b	cpu/x86/pae/pgtbl: Add memset with PAE ... To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation as well. Required for clearing all system memory as part of security API. Tested on wedge100s: Takes less than 2 seconds to clear 8GiB of DRAM. Tested on P8H61M-Pro: Takes less than 1 second to clear 4GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2019-07-02 08:45:50 +00:00
Xiang Wang	3d5bb2a5df	Documentatioan: update stage handoff protocol ... Change-Id: I170fc16675c2701f6ea133cfce6e5fabdfb0e8d3 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>	2019-06-21 09:28:56 +00:00
Patrick Rudolph	f04e76bcf0	Documentation: Add arch x86 ... Describe state and assuptions made about x86_64 support. Change-Id: I308a09b0eac269afd30df95ed3ea195238a6cfbe Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/30056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2018-12-19 10:31:07 +00:00
Paul Menzel	b06f8ddfe8	Documentation/riscv: Improve `index.md` ... 1. Add dot/period to the end of sentences 2. Remove blank line at the end of the file 3. Break lines after 75 characters 4. Use RISC-V spelling 5. Add comma for clarity Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/28654 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2018-10-30 02:10:44 +00:00
Jonathan Neuschäfer	d3037bdf64	Documentation: Add and link the arch directory ... Fixes: b159d5ba8f ("riscv: add documentation for stages and payloads") Change-Id: I5ca8ed094c9b6d115da707375205872e782a66b2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>	2018-10-11 01:22:21 +00:00
Ronald G. Minnich	b159d5ba8f	riscv: add documentation for stages and payloads ... Change-Id: Iff522e309e9cf9a31c1c79c24047d83d7fd0b00a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2018-09-15 12:52:32 +00:00