Commit Graph

11901 Commits

Author SHA1 Message Date
Duncan Laurie 25c6f75bb2 samus: Update for board revision 1.9
- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU

BUG=chrome-os-partner:28234
TEST=Boot on P1.9

Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201083
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6
Reviewed-on: http://review.coreboot.org/8007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:03:54 +01:00
Duncan Laurie fe8b788a12 samus: Move SPD related information to spd directory
Put all the SPD related information in one place including
the onboard SPD sources and the board specific parsing.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus

Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201082
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123
Reviewed-on: http://review.coreboot.org/8006
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:03:40 +01:00
Duncan Laurie 0aa06cbf18 wtm2: Convert to use soc/intel/broadwell
Convert wtm2 board to use the broadwell soc chipset.

BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2 with haswell and broadwell
CQ-DEPEND=CL:201067
CQ-DEPEND=CL:*164226

Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201070
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda
Reviewed-on: http://review.coreboot.org/8001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:03:17 +01:00
Patrick Georgi ab639bffc7 libpayload: don't test for unsigned >= 0
Change-Id: Ibeaf6de9505bc6f1e7358a4cfc80228dff7ddb69
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/7978
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-03 23:58:25 +01:00
Patrick Georgi 3cb56e934f libpayload: avoid memory overflows
With commands typically shorter than the buffer they're
copied to, copy cmdlen bytes, cut off by the buffer limit.

Change-Id: Ia9d2663bd145eff4538084ac1ef8850cfbcea924
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/7977
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-03 23:58:23 +01:00
Patrick Georgi 8180d1a22f libpayload/PDcurses: avoid NULL deref
Change-Id: I86f1c97858fa3d007c4d4509fac3473c9e2ad2f2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/7973
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-03 23:58:22 +01:00
Nicolas Reinecke dafa12adfc intel/model_206ax: update microcode
tested on ivy and sandy (t520/t420s & t530)

Change-Id: Ie527e8c4804821764ecc42f7495573eff67828f7
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7976
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-03 20:11:32 +01:00
Vadim Bendebury 24a53dddb9 ipq806x: clean up UART driver tx_byte function
The driver as it was copied from u-boot provided a function to
transmit multiple characters in one invocation. This feature was not
ported to coreboot, there is no need to maintain the complexity when
only one character at a time is transmitted. It is also very desirable
to get rid of a 1024 byte array allocated on the stack.

The array was necessary to allow to convert multiple newline
characters in the transmit data flow into two character sequences
CRLF. Now just a single word is enough to keep one or two characters
to transmit.

[EDIT km: newline translation is now part of printk]

BUG=chrome-os-partner:27784
TEST=verified that coreboot with the new code prints generates console
     output.

Original-Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201782
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit eab3dc9d30c7e8355a2563e18ada78e4070e6151)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4274b8f7188bf9636906b39bcd9ec7adf0e1222e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8011
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-03 20:02:37 +01:00
Hung-Te Lin 0780d67ffe util/cbfstool: Fix byte-ordering for payload type field.
In https://chromium-review.googlesource.com/181272 the payload->type has been
changed to big-endian (network ordering) but the cbfs_image is still parsing
type as host ordering, which caused printing cbfs image verbosely
(cbfstool imge print -v) to fail to find entry field and print numerous
garbage output.

Payload fields should be always parsed in big-endian (network ordering).

BUG=none
TEST=make; cbfstool image.bin print -v -v -v # see payloads correctly

Original-Change-Id: If1ac355b8847fb54988069f694bd2f317ce49a1a
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200158
Original-Reviewed-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 423f7dd28f8b071692d57401e144232d5ee2e479)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5a4694e887c7ff48d8d0713bb5808c29256141a9
Reviewed-on: http://review.coreboot.org/8005
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-03 17:33:13 +01:00
Kyösti Mälkki 3ae558f5a1 ARM64: Always has DYNAMIC_CBMEM
The static allocator only worked for x86 anyway.

Change-Id: Ibe4e172bb654f6414949bd11787c9407d091a858
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8028
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-03 06:25:52 +01:00
Kyösti Mälkki a38d1b2795 ARMv7: Always has DYNAMIC_CBMEM
The static allocator only worked for x86 anyway.

Change-Id: I0d2b63465620512e62334d7aa0c885fc5ab3e589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03 05:07:22 +01:00
Vadim Bendebury 96c9686407 storm: Put the page table at a correct address
The recently introduced page table location value is wrong, it
overlaps with other areas of the code. This patch fixes the location,
a more robust scheme is needed for memory layout management.

BUG=none
TEST=manual
  . occasional random failures disappear after this patch is applied

Original-Change-Id: Idc9047d38712736c5e8197e933c373488b333649
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202641
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit d26bb18e506680a1f481c3950007b2ea6a48e54d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7afcab42db259e53541fb991b36d680fc2186304
Reviewed-on: http://review.coreboot.org/8019
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-03 05:02:36 +01:00
Vadim Bendebury 1485c3040b storm: modify memory layout
This is an interim change (before EFS is enabled), align ROM and RAM
stages so that they have enough room and do not step over each other.

BUG=chrome-os-partner:27784
TEST=manual
   . booted coreboot successfully on ap148

Original-Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202046
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit f1fd4e3f9d699cc694cf7840c169db9bbe9193b6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9861d34a8bdd6963afbeed7fca7fda8a891ec481
Reviewed-on: http://review.coreboot.org/8012
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-03 05:02:07 +01:00
Deepa Dinamani 2c04117eac mainboard/storm: setup mmu in storm mainboard_init
enable protection of zero page access, provide for uncached device memory range,
and protect against access outside of DRAM except to device registers.

BUG=chrome-os-partner:28467
TEST=verified mmu.pagetable.list output:

_______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________|
     C:00000000--000FFFFF| | | | | | | | |
     C:00100000--3FFFFFFF| A:00:00100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered |
     C:40000000--428FFFFF| A:00:40000000--428FFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc |
     C:42900000--43CFFFFF| A:00:42900000--43CFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered |
     C:43D00000--5FFFFFFF| A:00:43D00000--5FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc |

Original-Change-Id: If9beb10938841aead5105d662f0aef741995d708
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200341
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 09dd137453d8c6f1b60692b01226498e22f34fb2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Conflicts:
	src/mainboard/google/storm/mainboard.c

Change-Id: Idff7e3f0bc5903933e9f1b980f595666380696d1
Reviewed-on: http://review.coreboot.org/8010
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03 05:01:08 +01:00
Deepa Dinamani 4d2d6ca79a soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.
Define a base address for page table entries. Place it 64KB below the
bootblock loading address.

BUG=chrome-os-partner:28467
TEST=verified that the page tables are being populated at this
     address. Also observed that the SPI driver takes 900 ns to
     process a byte as opposed to 1.5 us in case caching is not
     enabled.

Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200332
(cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068
Reviewed-on: http://review.coreboot.org/8009
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03 05:00:08 +01:00
Vadim Bendebury 41a5d0df58 ipq8064: add SOC initialization skeleton
The main benefit of adding this skeleton is the addition of the
correct memory map to CBMEM. Attempts to load depthcharge do not fail
because of unavailability of the bounce buffer.

BUG=chrome-os-partner:27784
TEST=boot updated firmware on AP148, observe

   CPU: Qualcomm 8064

  in the ramstage console output as well as not failing to load
  depthcharge any more.

Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199675
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013
Reviewed-on: http://review.coreboot.org/8000
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-03 04:59:50 +01:00
Vadim Bendebury 1ea5685862 storm: enable early console
Include the required modules in romstage and enable early console.

BUG=chrome-os-partner:27784
TEST=observe the romstage prompt in the console output:
   coreboot-4.0 romstage Tue May 13 17:08:58 PDT 2014 starting...

Original-Change-Id: Ie3853b9afc53246e6eb997f279ccd4dbb08f748b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199673
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 6e643d3425ee226b3ebfbf329b35e7017f83d0c3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibdc695da634356988b3e551b0a9e4be2e129ccb4
Reviewed-on: http://review.coreboot.org/7997
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 04:59:39 +01:00
Vadim Bendebury 15c98b0217 storm/ipq8064: add dynamic CBMEM support
Squashed the correction patch with the original to avoid confusion in
coreboot.org review.

All what's needed apart from configuring the feature is to provide a
function which would report the top of DRAM address.

BUG=chrome-os-partner:27784
TEST=manual
  . with all other patches applied, the image proceeds all the way to
    trying to download 'fallback/payload'.

Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3
Original-Reviewed-on: https://chromium-review.googlesource.com/197897
(cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

storm: initialize dynamic cbmem properly

Dynamic cbmem support has been enabled on storm, but the proper
initialization at romstage is missing.

Proper DRAM base address definition is also necessary so that CBMEM is
placed in the correct address range (presently at the top of DRAM).

BUG=chrome-os-partner:27784

TEST=build boot coreboot on ap148, observe the following in the
     console output:

  Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5
  coreboot table: 256 bytes.
  CBMEM ROOT  0. 5ffff000 00001000
  COREBOOT    1. 5fffd000 00002000

Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199674
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74
Reviewed-on: http://review.coreboot.org/7996
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 04:59:27 +01:00
Vadim Bendebury f3254348a1 ipq8064: Configure storm bootblock to run
This adds necessary configuration options to enable bootblock on Storm
to read the rombase image from the SPI flash.

BUG=chrome-os-partner:27784
TEST=manual
   . after this change is applied, the AP148 boots coreboot from the
     Spansion SPI flash device:

   coreboot-4.0 Thu May  1 14:25:34 PDT 2014 starting...
   Exception handlers installed.
   SF: Detected S25FL128S_256K with page size 10000, total 2000000
   CBFS: loading stage fallback/romstage @ 0x40608000 (7788 bytes), entry @ 0x40608001
   coreboot-4.0 Thu May  1 14:25:34 PDT 2014 booting...
   Exception handlers installed.
...

Original-Change-Id: I9d5e10d6e9f5b60bad5ea71003ea53d8c84ae188
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197801
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 73d72df228e3c6154d8836b0af6d94df91c88bf4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I509e6da15559c790f129d457d6e463ef90a5dc67
Reviewed-on: http://review.coreboot.org/7995
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 04:59:10 +01:00
Nicolas Reinecke 572795bf08 lenovo/t420s: Add new port.
This is based on x220 and t520. Tested on i7 model with usb3.
There is no support for nvidia gpu and optimus.

Change-Id: I6ca9436ccec3024095d02078e5e450147841e463
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7974
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-01-03 04:14:28 +01:00
Neil Chen c619c41890 blaze: change ramcode 1000/1001/1010 to use 792MHz bct
This change updates the cfg file for Hynix/Micron/Samsung 4GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.

BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.

Original-Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/202059
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 04e74d2fb0fefa6a1786225638380c8831bd9481)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6615e34a17bb372eda9dd0844ecddbcde902ad7c
Reviewed-on: http://review.coreboot.org/8008
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2015-01-03 00:56:17 +01:00
Vadim Bendebury 0e2d9b63d7 storm: ipq8064: enable CBFS SPI wrapper
This change forces storm platform to use the common CBFS SPI wrapper,
which makes the SOC specific CBFS code unnecessary and requires
including SPI controller support in all coreboot stages.

BUG=chrome-os-partner:27784
TEST=manual
  . with this change and the rest of the patches coreboot on AP148
    comes up all the way to attempting to boot the payload (reading
    earlier stages from the SPI flash along the way).

Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197932
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2
Reviewed-on: http://review.coreboot.org/7994
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 00:27:37 +01:00
Vadim Bendebury 20d3d53433 ipq8084: provide monotonic us timer
This service is required by various coreboot code modules. It looks
like the 8064 SOC does not provide anything better than a 32 KHz free
running counter (it is used in u-boot for us timer as well). Let's use
this for now.

BUG=chrome-os-partner:27784
TEST=manual
   . with the rest of the patches applied AP148 boots all the way to
     trying to start the payload.

Original-Change-Id: I98b91ce179f7388d59c769a59caf49ca7640e047
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197896
(cherry picked from commit d526830f9d9618e4ca3460165d7b9ecc8ab268cf)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id37ed21193db67ceee11a795713c34ef26383380
Reviewed-on: http://review.coreboot.org/7993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 00:27:09 +01:00
Julius Werner 989e12bb63 arm: Fix stored PC value when handling exceptions
ARM processors save the PC value in the Link Register when they handle
and exception, but they store it with an added offset (depending on the
exception type). In order to make crashes easier to read and correctly
support more complicated handlers in libpayload, this patch adjusts the
saved PC value on exception entry to correct for that offset.

(Note: The value that we now store is what ARM calls the "preferred
return address". For most exceptions this is the faulting instruction,
but for software interrupts (SWI) it is the instruction after that. This
is the way most programs like GDB expect the stored PC address to work,
so let's leave it at that.)

Numbers taken from the Architecture Reference Manual at the end of
section B1.8.3.

BRANCH=none
BUG=chrome-os-partner:18390
TEST=Provoked a data abort and an undefined instruction in both coreboot
and depthcharge, confirmed that the PC address was spot on.

Original-Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199844
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 4a914d36bb181d090f75b1414158846d40dc9bac)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib63ca973d5f037a879b4d4d258a4983160b67dd6
Reviewed-on: http://review.coreboot.org/7992
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-03 00:26:18 +01:00
David Hendricks 739e6a84aa elog: Add function to log boot reason in ChromeOS case
This adds a generic helper function for adding boot reason in the
ChromeOS case. If vboot is enabled, it will use information passed
in via the vboot handoff table in cbmem to determine mode and
reason in the case of recovery.

BUG=chromium:373467
BRANCH=nyan
TEST=built along with follow-up CL and booted on Big under various
modes, verified entry was added to eventlog with "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I50a7aa6d55eb46413fe9929e732d6eb18c758d4b
Original-Reviewed-on: https://chromium-review.googlesource.com/199690
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 961c0bd1dd5512b1c2feb2ed4391bf507900eb7a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6ae4e2a891966d2d1de7d37dcc551383e94e4d75
Reviewed-on: http://review.coreboot.org/7991
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-03 00:25:27 +01:00
Kyösti Mälkki 22261c387e allwinner/a10: Always has DYNAMIC_CBMEM
The static allocator only worked for x86 anyway.

Change-Id: Iadaab225fea04b455c559c25b918a2a842b9faca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8029
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-02 21:52:15 +01:00
Ronald G. Minnich 6d8228599b Allow RISCV to be compiled with ANY_TOOLCHAIN
Change-Id: I9210241c902ad8a88980a7c9cdb0d52c460b2541
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8025
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-01-02 18:44:57 +01:00
Ronald G. Minnich e8897c45a8 soc/riscv: Fix typo in src/soc/ucb/Makefile.inc.
riscv builds again.

Change-Id: I4caaee49c3eaa948540a916f684dd4e1ed9c9011
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8026
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-01 18:07:14 +01:00
Ronald G. Minnich 922b3ca8e5 ARM: Fix ARM_LPAE to not be selectable as a menu item.
It was showing up as a menu item and it should not.

Change-Id: I448f683fbf4187b11821381332f971b1daea29f8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-01 17:40:57 +01:00
Edward O'Callaghan 149ea15f7e mainboard/lenovo/t530/Kconfig: Enable VMX by default
Fix a trivial tab/space indent inconsistency while here.

Change-Id: I819d85293e1a070817cd13349a220ba85ba89951
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7984
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-01 05:35:19 +01:00
Duncan Laurie 2663a55caf samus: Combine mainboard patches to build soc/intel/broadwell
Combine four patches dependencies. These will not build
individually, so combine them for coreboot.org upstream.

samus: Move SPD handling to separate file

The code to find the SPD data for the mainboard based on GPIOs
is moved from romstage.c into spd.c.

It relies on the updated pei_data structure from broadwell instead
of the haswell interface.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Move PEI data structure init to separate file

This needs to be executed in both romstage and ramstage
for the different PEI binary stages.

It uses the broadwell interface now instead of haswell.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199921
(cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Convert mainboard to use soc/intel/broadwell

Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.

- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199922

(cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Add some code to print basic info from SPD

The handling of LPDDR is a bit messy in Intel platforms.  There
is no traditional SPD so instead one is created by hand from the
provided datasheets.

These have varying (and sometimes unexpected) geometry and it can
be important during bringup to know what configuration is being
passed to the memory training code.

This could in theory be put in a more generic location, but for now
this is the only board with LPDDR3 where I have found it valuable.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus, look for SPD details on the console.
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199923
(cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d
Reviewed-on: http://review.coreboot.org/7943
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31 21:24:48 +01:00
Duncan Laurie 229958e0b9 broadwell: Hook into the build system
Hook the soc/intel/broadwell directory into the configuration
and build system so it can be used by mainboards.

BUG=chrome-os-partner:28234
TEST=build and boot on wtm2

Original-Change-Id: Ia48ac644a8cefb2cf9c64efaa1bd9737ddfb8b1f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ee290d7f6e541999e077bcf871cd6c7b6504f3d6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iea5f37a839b516ac98227cc1737ce0d03f7e7e3b
Reviewed-on: http://review.coreboot.org/7940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31 21:23:09 +01:00
Marc Jones a6354a1aca broadwell: Preparations for building
Updated Intel Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.

- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic

Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-31 21:22:24 +01:00
Vadim Bendebury dffd892e47 ipq8064: modify SPI controller driver to work in coreboot
A typical SPI operation consists of two phases - command and data
transfers. Command transfer is always from the host to the chip (i.e.
is going in the 'write' direction), data transfer could be either read
or write.

We don't want the receive FIFO to be operating while the command phase
is in progress. A simple way to keep the receive FIFO shut down is to
not to enable it until the command phase is completed.

Selective control of the receive FIFO allows to consolidate the
receive and transmit functions in a single spi_xfer() function, as it
happens in other SPI controller drivers.

The FIFO FULL and FIFO NOT EMPTY conditions are used to decide if the
next byte can be written or received, respectively. While data is
being received the 0xFF bytes are transmitted per each received byte,
to keep the SPI bus clocking.

The data structure describing the three GSBI ports is moved from the
.h file into .c file. A version of the clrsetbits macro is added to
work with integer addresses instead of pointers.

BUG=chrome-os-partner:27784
TEST=not yet, but with the res of the changes the bootblock loads and
     starts the rombase section successfully.

Original-Change-Id: I78cd0054f1a8f5e1d7213f38ef8de31486238aba
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197779
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit c101ae306d182bbe14935ee139a25968388d745a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7f3fd0524ec6c10008ff514e8a8f1d14a700732f
Reviewed-on: http://review.coreboot.org/7983
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2014-12-31 21:05:50 +01:00
Vadim Bendebury 11c4c92d91 ipq8064/storm: UART enable and various fixes
The original patch from chromium was  a bit of a mishmash.
Between that, rebasing and using the coreboot.org UART infrastructure,
the patch has changed a bit from the original. It seems reasonable to
keep these changes together.
- build in the ipq UART and turn on bootblock console
- sets LPAE and ROM header address
- adds cpd.c to storm

The original commit:
ipq8064: make UART driver work in bootblock

This patch it the last one in the chain adapting the ipq9064 UART
driver for use in coreboot. A new config option
(CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of
the driver.

The previously introduced uart_wrapper.c is now included in the build
to provide the console driver structure used by ramstage.

Necessary configuration options are added to allow use of UART in the
bootblock.

BUG=chrome-os-partner:27784

TEST=with this change the coreboot image on AP148 prints a banner on
   start up:

coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting...

Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196663
(cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91
Reviewed-on: http://review.coreboot.org/7875
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-31 21:04:54 +01:00
Vadim Bendebury 19c3da5e64 libpayload: Do not tolerate compilation warnings when building
Make sure the build breaks in case of warnings.

BUG=none

TEST= All builds succeed with the restored patch and fail when a
      compilation warning is thrown.

Original-Change-Id: I9bdcd8938f59913e4ba86df5e4921b3f821ef920
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200110
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 16dde875950d6806cc770cdbee4d3ff456ed6f02)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I86988f8d3f1acaa6ceeabdcbfa3cede1e67c28fe
Reviewed-on: http://review.coreboot.org/7911
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-31 19:06:16 +01:00
Furquan Shaikh 79a591fb38 libpayload: Fix pointer related casts
Fix pointer related casts since this can create a problem for 64-bit systems.

BUG=None
BRANCH=None
TEST=Compiled successfully for link, nyan using emerge-* libpayload

Original-Change-Id: I4cbd2d9f1efaaac87c3eba69204337fd6893ed66
Original-Reviewed-on: https://chromium-review.googlesource.com/199564
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 914b118a64b0691aeca463dff24252db9c24109e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I11f070ed5d3eddd8b9be30c428cb24c8439e617b
Reviewed-on: http://review.coreboot.org/7905
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-31 18:57:35 +01:00
Edward O'Callaghan a40901bf01 vendorcode/amd/cimx/sbX00: Make SBPort.c filename consistent
Change-Id: I41ba4cffa545a31c1e0845ec44c8a433bda9f99d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7886
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-31 09:52:55 +01:00
Kyösti Mälkki bae775a4f4 arch/x86: Declare GDT symbols and move_gdt()
We relocate GDT to CBMEM, this can be done late in ramstage.
Note: We currently do this for BSP CPU only.

Change-Id: I626faaf22f846433f25ca2253d6a2a5230f50b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31 09:51:50 +01:00
Kyösti Mälkki a91e1e6cc1 Fix Kconfig whitespace
Change-Id: Iad64d018edda3064a77bfbcd41cfea5275a2e737
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8013
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-31 09:46:00 +01:00
Kane Chen d816a0251e baytrail: add more gpio init macros
GPIO init marcos are not enough to initialize different gpio attributes

BUG=none
TEST=emerge-rambi coreboot works well

Original-Change-Id: I193fa7b3e22632cacb555e726e3dd3991f4f4faa
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200531
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5e0fcbcd7cefcfccb5b565003336d197bb29e4cc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6bf4db9397733a003dfdedc6eb63b82127917851
Reviewed-on: http://review.coreboot.org/7953
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31 05:28:45 +01:00
Ken Chang a859aa3df5 nyan*: Set GEN2 I2C pads to open-drain mode
The VDDIO to GEN2 I2C SCL/SDA pins is 1.8V and the external
pull-up voltage is 3.3V (the external 3.3V > I/O 1.8V) thus
the pinmux E_OD bit of these two pins needs to be set to
ensure GEN2 I2C pads work fine on 3.3V.

BRANCH=nyan
BUG=none
TEST=observed voltage drop from 3.3V to 2.36V on gen2 i2c
on blaze w/o this change. the waveform looks good on both
scl/sda pins w/ this change.

Original-Change-Id: I1b97f0c9c7580d1e532c3bdf7ac8690241ee7ee3
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200996
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2db39166ec525e56a19746f38a867305a2687365)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0c84eade89311baf0a6f180cb5cc9e2145f6b7ea
Reviewed-on: http://review.coreboot.org/7952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31 05:26:51 +01:00
Vadim Bendebury 9e208bc357 Print segment clean up information only when required.
Eliminate duplicated printout and if needed, print only changed
information.

BUG=none
TEST=verified that the 'New segment dstaddr...' message is not
     duplicated anymore

Original-Change-Id: Ia13593394fccbb225f2bd9ab2b9228bac29d50fb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199672
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit aadf018821ebfa63d6ac9d2429ae1fb483dd6cb3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7544bddc4026191395cfe3b8ac66256ec223391e
Reviewed-on: http://review.coreboot.org/7937
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-31 05:26:27 +01:00
Shawn Nematbakhsh 0dadb767a0 rambi: Add _PRW for LID0 ACPI Device
The kernel will not track wakeup events for devices unless they have
a defined _PRW.  There is no EC output of the lid signal coming to
a GPIO and instead it pulses PCH_WAKE#.

BUG=chrome-os-partner:27631
TEST=Manual on Rambi.
- Run lidclose + lidopen on EC console, verify that wakeup_count
  increments.
- Run lidclose + lidopen in rapid succession, verify that suspend
  request is aborted.
BRANCH=Rambi.

Original-Change-Id: I8d4c58a7bb37d7e474ec094fe96e46e1bfd980de
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200289
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 08c6b42f1ed1af7fff6217e6b71469edd7ff4b2e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iee813ed6f39cd3d5e0a2bdd395c740f82a1cf01a
Reviewed-on: http://review.coreboot.org/7945
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31 05:26:01 +01:00
Sheng-Liang Song 8c7e62202d rambi: Unconditionally clear the EC recovery request
Implement Rambi clear_recovery_mode_switch()

BUG=chromium:279607
BRANCH=TOT
TEST=Verified recovery sequences on Rambi.

Original-Change-Id: I481329d0f49584ad0314bd982b80bbc86112c2c0
Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197781
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Sheng-liang Song <ssl@google.com>
Original-Tested-by: Sheng-liang Song <ssl@google.com>
(cherry picked from commit 77e60a039f3d8328694a743e7cd15cce71b02f5d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I837151551b8aa68cf86b6fa1dd39b7b673d6a4d9
Reviewed-on: http://review.coreboot.org/7896
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2014-12-31 05:25:44 +01:00
Rajmohan Mani d6fb32b461 libpayload: usb: xhci: Fix TD size if it overflows 5 bits
xHCI Spec says TD Size (5 bits) field shall be forced to 31,
if the number of packets to be scheduled is greater than 31.

BUG=chrome-os-partner:27837
BRANCH=rambi,nyan
TEST=Manual: Ensure recovery boot with USB 2.0 media on Squawks
works fine without any babble errors.

Original-Change-Id: Iff14000e2a0ca1b28c49d0da921dbb2a350a1bbd
Original-Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Original-Originally-Reviewed-on: https://chromium-review.googlesource.com/202297
Original-Reviewed-on: https://chromium-review.googlesource.com/202330
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit ae58b99370df3a86bf15d84b97db858a968b1dbd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9668b947f676c109fad9297e5efde91bf7f796fd
Reviewed-on: http://review.coreboot.org/7913
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-31 04:45:43 +01:00
Sheng-Liang Song 1d6560fc60 chromeos: Unconditionally clear the EC recovery request
Add the empty weak function clear_recovery_mode_switch().

Problem:
If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is set,
the following will happen:

1. Boot device in recovery mode with Esc + F3 + Pwr.
2. Turn device off with Pwr button.
3. Turn device on with Pwr button.

Device still boots to recovery screen with
recovery_reason:0x02 recovery button pressed.

If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC isn't set, turning the
device off and on again  with the Pwr button does a normal boot.

Solution:
Unconditionally clear the recovery flag.

BUG=chromium:279607
BRANCH=TOT
TEST=Compile OK.

Original-Change-Id: Ie1e3251a6db12e75e385220e9d3791078393b1bf
Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197780
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Sheng-liang Song <ssl@google.com>
Original-Tested-by: Sheng-liang Song <ssl@google.com>
(cherry picked from commit 18908bb64cef34ca41812814817ef887961bed34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I71ca9f3ea8d816c865375ec66a0603ca211f23ae
Reviewed-on: http://review.coreboot.org/7895
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-30 23:30:52 +01:00
Daisuke Nojiri afde961adf vboot: Convert response_length from uint32_t to size_t in VbExTpmSendReceive
Length arguments for VbExTpmSendReceive have type uint32_t but it calls function
which expects size_t. This change converts uint32_t to size_t on call and
size_t to uint32_t on return.

BUG=None
BRANCH=None
TEST=Booted Nyan Big to Linux

Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I1971488baae2d060c0cddec7749461c91602a4f9
Original-Reviewed-on: https://chromium-review.googlesource.com/198016
(cherry picked from commit 6830747eb47568f2a2b494624522d37d8945c030)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I20741759e7bbd60dd7044c532287d6b55047e19a
Reviewed-on: http://review.coreboot.org/7894
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 22:44:24 +01:00
Kein Yuan 704c006479 Rambi: Set SOC_DISP_ON as GPIO to avoid LCD_VCC glitch
To avoid LCD_VCC glitch on cold reset, set SOC_DISP_ON as GPIO output high.
After gfx initialize is done, set it to native function 2.

BUG=chrome-os-partner:25159
BRANCH=firmware-rambi-5216.B
TEST=Tested on Rambi and squawks, no LCD_VCC glitch anymore.

Original-Change-Id: If16af498e910a8da1d77a9a66456eb767286a61a
Original-Change-Id: Icf62588fa0338f89fafb3fe9246c26f16bcdaa60
Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197985
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 6f7d621678f22133c9825565fedc77d19198b08c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibaf547b8d1c27811a1bec9fa3254d559c505a361
Reviewed-on: http://review.coreboot.org/7893
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-30 22:44:09 +01:00
Duncan Laurie 4397aa1347 vboot: Add a new post code for TPM failure
If the kernel does not properly handle the TPM and send it a
TPM_SaveState command before suspend then it will not be in
the correct state on resume.  In order to easily detect this
case add a new post code for TPM failure and use it in the
vboot resume path.

BUG=chromium:371105
TEST=Build and boot on wtm2.

Original-Change-Id: I412520b521387a8e18ad1c6f5a64b39cdd5c88ec
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199371
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ff2f0dc56c1a783295710f81567af02729fe1da2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5baf894fd72922acd79d191e5485ae8ef7e0d559
Reviewed-on: http://review.coreboot.org/7936
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 22:13:30 +01:00