Where vboot verification can start, and how the code flow looks like is more a
property of the SoC (and its properties, like amount of SRAM) rather than the
board.
Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10662
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Otherwise it'll determine some offsets from uninitialized data and hilarity
ensues.
Change-Id: I6a671987857cfd3f3cd6078aebd13dd09fc79020
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10660
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
vboot requires it.
Change-Id: Iae2310c9b9c311c3f64b8417295685261ba404b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With an x86_64-elf toolchain, this code that is unused
outside of ramstage, is causing undefined references.
Help the compiler along a little bit by conditionally compiling
the code in ramstage only.
Change-Id: I75518149b53c24eda4b985b0fef856447e196dec
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Restrict the use of the common romstage/ramstage code to FSP 1.1
BRANCH=none
BUG=None
TEST=Build and run on cyan/sklrvp
Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10653
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the copyright address from all of the files.
BRANCH=none
BUG=None
TEST=None
Change-Id: I7190e34e165e5652d33902440fa08253b77f4af2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10337
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the files to support the Braswell SOC.
BRANCH=none
BUG=None
TEST=Build for a Braswell platform
Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Because of a missing close quote, we have the warning:
src/soc/intel/common/Kconfig:52:warning:multi-line strings not supported
This was added in commit 0946ec37 -Intel Common SOC:Add romstage support
The whitespace issue - using spaces instead of a leading tab was added
in the same commit.
Change-Id: I429c66afb5a7e10ca0e0ef619ac46722c63fb376
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10654
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Besides the first five DWORDs, the offsets 0x40 & 0x41
are used to save SPI settings. They should only be 0xFF
for being written.
Other parts in ROMSIG are also changed to 0xFF for potential
requirement.
Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10651
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Move the 'Intel FSP' Kconfig comment inside the 'if' block so that it
doesn't show up on platforms that aren't using it.
- Update the comment to reflect that this is version 1.1 of the FSP
interface.
Change-Id: I7182c5b07332c4f95620f7374526ab1de0484d01
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10650
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Provide a common romstage implementation for the Intel SOCs.
BRANCH=none
BUG=None
TEST=Build for Braswell
Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use 3rdparty/blobs subdirectory for binary files
Display the MTRRs after TempRamExit and before the MTRR setup
Clear all of the variable MTRRs before the MTRR setup
Define the FSP attributes location and bits
Properly display the FSP_RESERVED_MEMORY_RESOURCE_HOB and the
FSP_BOOTLOADER_TOLUM_HOB.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I788a5f1e7676b1a06c1bcd66ddbd0a2249cad47c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=None
TEST=Build and run on strago
Change-Id: Ia3740353eb16f2a2192cad8c45645f845bf39475
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10588
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add new GUID for FSP.
BRANCH=none
BUG=None
TEST=Build and run on strago
Change-Id: I539a59b513f67535436f581e0a79ab53f05682ca
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10587
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.
Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10640
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
I looked for a way to pass the 'make crossgcc -j8' on to buildgcc, but
didn't find a way to get that value directly. MAKEFLAGS turns -j8 into
a jobserver variable.
Instead, this patch allows the number of CPUs to be set on the command
line through a variable instead.
Example: 'make crossgcc BUILDJOBS=8'
Change-Id: I37608cdb4549226cb7ff8c3ff6d9f4773acf6b0b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10620
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update the clean target to remove the intermediate files. These should
get removed automatically, but if the build stops in the middle, or if
the -t command is used for buildgcc, they can be left in the directory.
Add a distclean target that removes the downloaded tarballs as well as
everything else.
Change-Id: I6ea19e7a499b0c313c1d2eff7e36386204ec834e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10621
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
CAR_MIGRATION was removed in commit:
cbf5bdfe - CBMEM: Always select CAR_MIGRATION
ALT_CBFS_LOAD_PAYLOAD was removed in commit:
cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD
MARK_GRAPHICS_MEM_WRCOMB was removed in commit:
30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB.
EXTERNAL_MRC_BLOB was removed in commit:
0aede118 - Drop unused EXTERNAL_MRC_BLOB
CACHE_ROM is only in Google's codebase.
LID_SWITCH is only in Google's codebase.
DEFAULT_POST_DEVICE_LPC is only in Sage's codebase.
ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used.
HUDSON_NOT_LEGACY_FREE never existed as far as I can tell.
MAINBOARD_DO_EDID never existed as far as I can tell.
Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10616
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
After commit with Change-Id Ia1839ed3 (sandy/ivy: Include
IRQ routes from platform), update autoport to include
that file into the DSDT.
Change-Id: I14534438d0b433895f384539c8b413eaa53d943a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10612
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The default route does work for all Chromebooks and is replaced
with platform-specific one in follow-up.
Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10442
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I0796b6e7adad0151c5aa6271d62a2cf4abeedb1e
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC.
This is the start of creating a common interface for all of them.
This also allows us to reduce the chipset dependencies for CBFS_SIZE.
Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10613
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bring back the ability to link in the DSDT. This is to help Chrome OS to
switch over to a new upstream quickly (because some of the custom built
mechanisms are a pain with tons of files).
This is supposed to be temporary (famous last words), but I'd rather fix the
lack of CBFS awareness in CrOS bit for good in the time I usually spend on
keeping upstream and CrOS branches close.
Change-Id: I7fa5540bbf5c568c4adca56a09c83b6c7e358ad5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is only needed on boards that still provide old style PIRQ
tables.
Change-Id: Ie299de2937e5b91b7b3e1d1110e40be23c6d9f52
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10508
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Otherwise per default git will attempt to push to the blobs
repository directly instead of sending commits to gerrit.
Change-Id: I2ba241e0040a9c749c5bedc3d45d00b0b0dbe9e9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10537
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
AMD Kern uses PspSecureOs_prod_CZ.csbin rather than PspSecureOs_prod_CZ.sbin.
PspSecureOs_prod_CZ.csbin is the firmware in CarrizoPI v1.0.0.7.
Change-Id: Idf54ee808dd6965aec9b979be00b7f890a88b06d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10639
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The CBFS size is really mainboard specific, since it really depends on
size of the chip on the mainboard, so it makes sense to have it in
the mainboard menu along with the ROM-chip size.
- Move the CBFS_SIZE definition up in src/kconfig
- Move the Mainboard Menu markers out of src/mainboard/kconfig into
src/Kconfig so CBFS_SIZE can live in the mainboard menu.
- Add a long list setting default values to do what the chipset
directories were previously defaulting the values to. This will
be trimmed down in a following patch that creates a common set of
IFD routines. (Who knew that kconfig supported line wrapping?)
- Update the help text.
Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10610
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
SeaBIOS uses a version string which is derived from hostname.
Defining our own version strings drops this dependency.
This only works in versions newer than rel-1.8.0-36-g624e812.
Change-Id: Ie800deffd3706d1b2dabf5258e2e48bfcd2929b7
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/10515
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
- Move IASL up with the other tools.
- Remove OUT= which is no longer used in the
payloads/external/SeaBIOS Makefile.
Change-Id: I211ddcf3496b533151936fa5cbfa7a92986ec28f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Allow adding and executing a refcode binary.
Change-Id: I00e91a088a5695b42528e246d0ed642d988603e3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's guarded by a non-standard configuration option, so didn't trigger.
Change-Id: Ib7a9a45befcb7857edde37e20de7d65a60970882
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10623
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Mickey:
- Does not have power key
- Does not have an audio codec(all audio goes thru HDMI)
- VCC18_LCD moved to VLDO8 and needs to be turned on (was
connected to VSWOUT2 earlier)
BUG=none
BRANCH=none
TEST=Boot from mickey board, and hdmi work normal
Change-Id: I88cdc41ce8bb96a6b17aeb7f24b1c5619471b24e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c966edfa29df1049c469442dc3ad8bf8b4197b1
Original-Change-Id: I3d98203185f52ed751a5d3045a0ee8f9b4dfbc71
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274876
Reviewed-on: http://review.coreboot.org/10630
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
VPD strings are not null terminated, so we can't use strcpy
on them in cros_vpd_gets.
BUG=none
BRANCH=none
TEST=add serial_number followed by cam_calib_data to VPD on smaug;
make sure that smaug boots and serial number matches exactly (no garbage)
Change-Id: Id72885517b3d0b1934ba329c1ef0d89a67bd2bb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 56bbe6688b11043360a046a250d1ea93db4d9f0e
Original-Change-Id: I811dfc2f0830a91410eb69961a6565080ff78267
Original-Signed-off-by: Stephen Barber <smbarber@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280836
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: http://review.coreboot.org/10627
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
They're ASCII only, with only one language at a time,
but they should be good enough to report device names and
serial numbers.
BUG=none
BRANCH=none
TEST=with depthcharge CL, check dmesg on the host device
Change-Id: If888e05b2f372f7f0f43fadb108ca7ef4ed3b7c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f0bc4242057d3edc4f4796ebeed2d98d89d60a1d
Original-Change-Id: Ibe42f1b49f412e5482cebb7ebe20f6034352fd12
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/278300
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10626
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
this is an brief hdmi driver which config with simple
display parameter, const encoder input & output color
format and 8bit color depth, and only 48KHz audio support.
what's more to prevent TV have not show an right things
before coreboot switch to kernel space, we have to add
an terrible 2s delay to driver (2s come from test many
times), cause we have to wait TV to respond (we got no
flag to check whether it is ready).
BUG=chrome-os-partner:40337
TEST=Booted Veyron Jerry and display normal
BRANCH=None
Change-Id: Icd33467e95de6219e1b614616f0112afc52097b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e5b699aff75a579116aae63d858c834b2f648e8
Original-Change-Id: Iedc87c011c5b62ce5f16a296dd9c3e0c2eaba59b
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272565
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I080c0a5954d3e4b2d6debdf2a77f32df7329841c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Patrick Georgi