Commit Graph

54785 Commits

Author SHA1 Message Date
Paul Menzel 274d509596 MAINTAINERS: Spell Jérémy’s name with accents
Change-Id: I4c025bbcb205fa5bd3dcb35c685a3db289a3f824
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78803
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 16:38:56 +00:00
Felix Singer 1b102cae36 mb/system76/adl/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I2f641ce1fc44a9d7c9f9c403d255997214021f47
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-10-30 14:01:12 +00:00
Felix Singer 983b169a36 mb/system76/rpl/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I15f326774850b3c9562f7eebb78f29430dec1031
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78667
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 14:00:59 +00:00
Felix Singer ee1fd54aef mb/system76/{tgl,skl}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 14:00:48 +00:00
Felix Singer d163253ba0 mb/system76/cannonlake/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 14:00:37 +00:00
Matt DeVillier 1fd4d76043 mb/google/hatch/var/palkia: Use chipset devicetree references
Switch palkia overridetree to use chipset devicetree references.

Change-Id: Ic5fd2d139d22824d3ada09325022c37e69b5e2a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30 13:48:38 +00:00
Matt DeVillier b0b659adf1 mb/google/hatch/var/nightfury: Use chipset devicetree references
Switch nightfury overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.

Change-Id: I9bb028ad12b97fd4510f6d1026fdc16232c64dba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78570
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 13:44:10 +00:00
Matt DeVillier 690e255731 mb/google/hatch/var/mushu: Use chipset devicetree references
Switch mushu overridetree to use chipset devicetree references.

Change-Id: Iac05b0b2c5785f2cb69a29aa4d4c3088f164385f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30 13:43:54 +00:00
Matt DeVillier 7f74f9de27 mb/google/hatch/var/kohaku: Use chipset devicetree references
Switch kohaku overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.

Change-Id: Idcfde6882fc433e6a248aff6baf23b1a5bf7d201
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30 13:43:45 +00:00
wuyang5 b621e08ed4 mb/google/corsola: Add new board 'Chinchou'
Add a new Krabby follower 'Chinchou'.

BUG=b:307161347
TEST=make # select Chinchou

Change-Id: Ic90f85621598ab253d3ec9fe44aa076712248223
Signed-off-by: wuyang5 <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78596
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 07:28:07 +00:00
Jeremy Compostella 66df100930 cbfstool: Fix CBFS header buffer overflow
In the unlikely but possible event where the name of the CBFS file is
longer than 232 characters, `cbfs_create_file_header()' would overflow
the buffer it allocated when it copies the CBFS filename.

Change-Id: If1825b5af21f7a20ce2a7ccb2d45b195c2fb67b0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-29 14:23:23 +00:00
Sumeet Pawnikar 3e57c57480 mb/google/brya/variants/craask: Enable DDR RFIM Policy for Craask
DDR interfaces emit electromagnetic radiation which can couple
to the antennas of various radios that are integrated in the system,
and cause radio frequency interference (RFI). The DDR Radio Frequency
Interference Mitigation (DDR RFIM) feature is primarily aimed at
resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies
for the Wi-Fi high and ultra-high bands (~5-7 GHz).
This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature
for Craask variant.
Refer to Intel doc:640438 and doc:690608 for more details.

BUG=None
BRANCH=None
TEST=Build and boot Craask.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I5560bbedb26e88edd9d35f16b639fe63ef42c30e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-29 14:21:58 +00:00
Bill XIE c557847a9e mb/lenovo/t430: Disable SuperSpeed capabilities for WWAN USB
Just as in commit 38569d061099: ("mb/lenovo/{x230, x230s}: Disable
SuperSpeed capabilities for WWAN USB")

Although on ThinkPads with Panther Point PCH the usb port inside wwan
socket is usually wired to XHCI, it has actually no SuperSpeed lines,
so maybe it is okay to disable SuperSpeed capabilities, and wire them
to EHCI #2 by making use of XUSB2PRM and USB3PRM.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I61e61283a821686558f7f3fdfac7073bb3557e93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78680
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-29 14:21:02 +00:00
Arthur Heymans a6cfb336f2 payloads/LinuxBoot: Add uImage to clean target
uImages are generated for non-x86 arch.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Icb1184497087d66a7cc6fd27402365a028cc4eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-10-28 21:05:48 +00:00
Marx Wang be0e694fcf soc/intel/meteorlake: Expose In-Band ECC UPD config to mainboard
Meteor Lake has a UPD config called In-Band ECC(IBECC) which uses a part of the system DRAM to store the ECC information. There are a few UPD parameters in FSP-M to configure this feature as needed.

This patch adds code to expose these parameters to the devicetree so
that they can be configured on the mainboard level as needed.

Change-Id: Ice1ede430d36dff4175a92941ee85cc933fa56d5
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28 21:02:09 +00:00
Jeremy Compostella e68650a656 vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header file
Export Power State Current 1, 2 and 3 Threshold configuration entries.

BUG=b:308002192

Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-28 20:57:52 +00:00
Kane Chen 648ed149a1 mb/google/rex: add dptf settings for 2+4 SOC SKU
This patches privides settings based on 2+8 15w.

BUG=b:306543967
TEST=boot on rex with 2+4 SOC and power limit settings are overridden
correctly in variant_update_cpu_power_limits

Change-Id: I0560e44ce8e0d91bb5fb9c7cc9ffe68ab050bf00
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78688
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-28 20:57:09 +00:00
Kane Chen 6feb1de20a soc/intel/meteoerlake: Add power limits for 2+4 15W SOC SKU
This commit adds power limit settings for 2+4 15w SOC sku and renames
MTL_P_282_CORE to MTL_P_282_242_CORE since they are sharing same 15w
settings.

BUG=b:306543967
TEST=boot on rex with 2+4 SOC and power limit settings are correct

Change-Id: Id738303d1652f964142f8f27110426d6b84609bf
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78495
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 20:56:53 +00:00
Jeremy Compostella d4bf7211ca mb/google/rex/var/rex0: Configure EN_WWAN_PWR GPIO based on CBI
GPP_B17 (aka. EN_WWAN_PWR) should be kept low when the device does not
have a WWAN module.

TEST=Power consumption drops to 0 in S0iX

Change-Id: I95150c20c98b037a47827a7b83e4373c6e9070e3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78684
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-28 20:56:11 +00:00
Morris Hsu 0ec65daf7d mb/google/brya/var/dochi: Update overridetree for touchscreen
Update overridetree for ILI2901 and eKTH7B18U touchscreen.

BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot

Change-Id: Ib45f3c7c92ea525ca13a6137dd87eeb318f30384
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
2023-10-28 20:55:45 +00:00
Patrick Georgi 3d295a9afb util/cbfstool: Enable "ms-extensions" compiler flag on mingw only
The flag activates some Win32 compatibility quirks and on
clang/openbsd it enables so many of them that the code doesn't compile
anymore. Therefore move it into the "Win32 area" in that Makefile.

Change-Id: Ic77c04941e40a568f1d74cec09eb3d22a66e69b0
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78724
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 19:57:53 +00:00
Felix Singer 9a1b47e8a0 mb/{sm/x11,razor,libretrend}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.

While on it, remove superfluous comments related to modified lines.

Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28 18:42:46 +00:00
Matt DeVillier d5008a2e82 mb/google/zork: Clean up Kconfig entries
Alphabetize board entries, Kconfig selections, and config options.

Change-Id: I94e6e584809888fc9cab1b4cff6c0368803c1d47
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-10-28 18:30:15 +00:00
Matt DeVillier d59f9f6e69 mb/google/zork/Kconfig.name: Alphabetize board entries
Change-Id: I6843fd2eb752cd35d8c67ad7487f6dbb1c1afc62
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78707
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-10-28 18:29:58 +00:00
Matt DeVillier baa1d82322 mb/google/guybrush: Clean up Kconfig entries
Alphabetize board entries, Kconfig selections, and config options.

Change-Id: I599eda8c136d072471f022be9397faeb0e061472
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78706
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 18:29:33 +00:00
Matt DeVillier a05be2d1fb mb/google/guybrush/Kconfig.name: Alphabetize entries, add names
Alphabetize entries and add consumer product names for boards where
available.

Change-Id: I22a18ba85d6ff203765f984fba51784757a2a4df
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78705
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 18:29:22 +00:00
Matt DeVillier cea9415079 mb/google/skyrim: Clean up Kconfig entries
Alphabetize board entries, Kconfig selections, and config options.
Reverse default logic of PERFORM_SPL_FUSING for simplicity / clarity.

Change-Id: Ib25bb8c7bbf994f2f0675c4599c70a7db5d9f7ef
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-28 18:28:59 +00:00
Matt DeVillier 2a8c71c11b mb/google/skyrim/Kconfig.name: Alphabetize entries, add names
Alphabetize entries and add consumer product names for boards where
available.

Change-Id: I7459ee0a63025c12c7dbe75c578c7496c49fa475
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-28 18:28:41 +00:00
Nicholas Sudsgaard 9f5902f7e9 doc/lib/flashmap: Fix incorrect path to FMD implementation
Change-Id: I6864cd041d7173cd284f47d09f4388341a7ee756
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78690
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 14:30:46 +00:00
Subrata Banik 8c4674ee37 mb/google/{rex, ovis}: Introduce devicetree.cb for pre-prod SoC
This patch introduces a dedicated devicetree.cb file for platforms
built with pre-production SoC. This will help to keep the SoC
configuration separate for platforms with ESx and QSx silicons.

For example, the SaGv WP configuration is different between
pre-production (aka ESx) and production (aka QSx) silicon.

BUG=b:306267652
TEST=Able to build and boot google/rex4es.

Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
2023-10-28 05:40:52 +00:00
Matt DeVillier 830b0ac4e1 mb/google/hatch/var/*: Disable unused device in SerialIO cfg
For variants without a digitizer, disable I2C2.
For variants without a proximity sensor, disable I2C3.
For variants without a fingerprint reader, disable SPI1.
For all variants, disable I2C5 as it is unused.

Adjust comment blocks as needed.

Change-Id: I27e9eb2b0dcc869d1964c0b17c656d6691c0f05e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78553
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27 23:38:07 +00:00
Matt DeVillier d7a8da36ae mb/google/hatch/var/jinlon: Use chipset devicetree references
Switch jinlon overridetree to use chipset devicetree references.

Change-Id: I663a1d051d287f8484c5d4d175337f4f24081044
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-27 23:37:26 +00:00
Matt DeVillier c70fbb0e95 mb/google/hatch/var/kindred: Use chipset devicetree references
Switch kindred overridetree to use chipset devicetree references.

Change-Id: I2c54406948d2db53d25aa7c3dc79cfb5661c4a69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78564
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27 23:37:15 +00:00
Mark Hsieh 926be77361 mb/google/nissa/var/joxer: Override tdp pl1 value for DTT tuning
Follow thermal validation, override tdp pl1 in 6w ADL_N platform to
10w and override tdp pl1 in 15w ADL_N platform to 20w.

BUG=b:307365403
TEST=USE="project_joxer emerge-nissa coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I8dd743e65b9e5fbd6aa2fd9c1b87c7bd487c8174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78650
Reviewed-by: ChiaLing <chia-ling.hou@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
2023-10-27 17:21:20 +00:00
Martin Roth face29cd50 security/intel/stm: Remove check that can never be true
STM_RSC_MEM_DESC defines rws_attributes as 3 bits, which can't be
greater than 7.

Found-by: Coverity Scan #1430578
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1efd007e96abd6d5d36f314752abfadffb0024d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-27 17:20:09 +00:00
Felix Singer cc93db9435 mb/intel/skylake/devicetree: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.

While on it, remove superfluous comments related to modified lines.

Change-Id: I769233a5baabbea920c9085f8008071ba34bb9dd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78598
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27 16:34:23 +00:00
Martin Roth 7a4583a417 Kconfig: Add vendorcode debug
This includes Kconfig.debug files under vendorcode into the debugging
menu. Currently it's being added to pull vc/amd/opensil/Kconfig.debug
in.

Change-Id: Ie7c8235354ea5a0b156dcbb147d35c157fbd14da
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-27 15:39:47 +00:00
Felix Held 926887ced9 soc/amd/genoa: add PCI domain resource reporting
Use the common AMD data fabric resource reporting code to report how
openSIL distributed PCI buses, MMIO, and IO resources to coreboot's
resource allocator. This replaces the original CB:76521 which was
written back when the common AMD data fabric resource reporting code
didn't exist yet.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ifcd655ea6d5565668ffee36d0d022b2b711c0b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-10-27 12:34:23 +00:00
Felix Held 0f209b58d2 soc/amd/genoa: select PSP gen 2 support
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iffe21fb0c0bff0fc21ce1ac3af71d39bb62fd384
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78660
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27 12:33:23 +00:00
Anil Kumar 66fb5181e3 mb/google/rex: Update FMD to support CBFS verification
This patch adds the required FMD changes to support the change
in cse_lite 'commit Ie0266e50463926b8d377825 ("remove
cbfs_unverified_area_map() API in cse_lite")' for CBFS verification.

These blobs were kept separate originally to avoid hash loading and
verification every time and hence save boot time.

With the change in cse_lite the ME_RW_A/B blobs are now part of
FW_MAIN_A/B and corresponding entries in FMD can be removed.

BUG=b:284382452
TEST=Build CB image for google/rex board and test CSE FW
update/downgrade with CONFIG_VBOOT_CBFS_INTEGRATION config enabled.
Also confirm there is no increase in boot time with this change.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I56865a9e5c8b5f9e908e00e1a7e7e187d5d6a2f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-27 06:38:50 +00:00
Rizwan Qureshi d81d80c554 soc/intel/cse: remove cbfs_unverified_area_map() API in cse_lite
With CBFS verification feature (CONFIG_VBOOT_CBFS_INTEGRATION)
being enabled, we can now remove cbfs_unverified_area_map() APIs
which are potential cause of security issues as they skip verification.

These APIs were used earlier to skip verification and hence save
boot time. With CBFS verification enabled, the files are verified
only when being loaded so we can now use cbfs_cbmem_alloc()/cbfs_map
function to load them.

BUG=b:284382452
Change-Id: Ie0266e50463926b8d377825142afda7f44754eb7
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78214
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-10-27 06:37:35 +00:00
Shelley Chen 952a4473ec mb/google/brox: Add Arbitrage generated gpio.c file
Checking in gpio.c generated by arbitrage.  Used this command line to
generate:
    arb export-coreboot-gpio --refdes=U1 brox:proto1_20231017

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I1098bd4cfde393ed9e78cd90158c3534fdf0dc09
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78657
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26 20:28:36 +00:00
Shelley Chen 492727145a mb/google/brox: use Alderlake-P SoC instead of Alderlake-S
Skolas is actually using the SOC_INTEL_ALDERLAKE_PCH_P config, so
fixing Brox to reflect this as it's using the same SoC.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I632ec055d523956983d2053cd8e7000b1eaabf92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78656
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26 20:28:18 +00:00
Matt DeVillier b9165199c3 mb/prodrive/hermes: Rework UART devicetree entry
Rework the UART devicetree entry so that it doesn't conflict with the
to-be-added chipset devicetree for CNL. This should be functionally
equivalent to the previous entry, but needs testing to verify.

Change-Id: Iae60cb8e0746e7dc2928da3687762b81928fb5f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78546
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-26 18:35:57 +00:00
Matt DeVillier 14701fb6a6 mb/google/hatch/baseboard: Use chipset devicetree references
Switch baseboard devicetree to use chipset devicetree references.
Drop any devices whose status (on/off/hidden) matches the default
in the chipset DT.

TEST=build/boot google/hatch (akemi)

Change-Id: I5954c304f3c0e04be7e061c1c23a278f81b6ff4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-26 18:02:24 +00:00
Matt DeVillier 859a781705 soc/intel/cannonlake: Add/use chipset devicetrees
Change-Id: I8ceae832e60cd3094b4a34ab3a279e5a011f2c80
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-26 18:01:29 +00:00
Matt DeVillier 1dd435c630 mb/google/hatch/var/helios_diskswap: Use chipset devicetree references
Switch helios_diskswap overridetree to use chipset devicetree references.

Change-Id: I0a3385139c74a59c2006b8963850d00ee39f70a8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78560
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26 17:46:47 +00:00
Matt DeVillier 0b1030e494 mb/google/hatch/var/helios: Use chipset devicetree references
Switch helios overridetree to use chipset devicetree references.

Change-Id: If7901066a0c77231779eb298dc40962d8ac62814
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26 17:46:00 +00:00
Matt DeVillier 6841e63b46 mb/google/hatch/var/hatch: Use chipset devicetree references
Switch hatch overridetree to use chipset devicetree references.

Change-Id: Icccb433ba3e5a1ecb192f8db830674047e801623
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26 17:45:18 +00:00
Matt DeVillier df6473f2c6 mb/google/hatch/var/dratini: Use chipset devicetree references
Switch dratini overridetree to use chipset devicetree references.

Change-Id: I9f365077291ee9fa5f4dcf8835756f4cfd6eeab4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26 17:44:52 +00:00