Commit Graph

15470 Commits

Author SHA1 Message Date
Timothy Pearson 919d9ba633 mainboard/asus/kgpe-d16: Add nvram option to enable/disable IEEE 1394
Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11947
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-29 20:21:57 +01:00
Patrick Georgi 8f5053c626 util/fuzz-tests: Add fuzzer for jpeg decoder
Mostly a proof of concept for adding fuzzing to our tree.

Change-Id: I10e5ef3a426b9c74c288d7232a6d11a1ca59833b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/12183
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-29 19:00:42 +01:00
Aaron Durbin 5907eb8f5a commonlib/region: add xlate_region_device
There are cases where one region_device needs to be
accessed using offset/sizes from one address space
that need the offset translated into a different
address space for operations to take place. The
xlate_region_device provides an offset that is
subtracted from the incoming transaction before
deferring to the backing access region.

Change-Id: I41d43924bb6fbc7b4d3681877543209e1085e15c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12227
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-29 18:58:07 +01:00
Patrick Rudolph e11f6c3be1 nb/intel/sandybridge/gma: add disable function
Issue observed:
In a multi GPU setup (IGD and PEG) the system still uses the IGD.
CONFIG_ONBOARD_VGA_IS_PRIMARY has no effect on Sandy/Ivy Bridge.

Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
* ATI Radeon HD4780

Problem description:
The GMA is missing a disable function.

Problem solution:
Add a GMA disable function. Deactivate PCI device until remaining multi
GPU issues are resolved. Do not claim VGA decode any more.

Final testing results:
The system is able to boot using the PEG device as primary VGA
device.

Change-Id: I52af32df41ca22f808b119f3a4099849c74068b3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11919
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-29 17:08:48 +01:00
Paul Menzel 114a9489ed amd/cimx/sb800/late.c: Add comment in `sb800_init()`
Add a comment explaining what `abcfg_reg(0xc0, 0x01FF, 0x0F4)` does.
This is a follow-up for commit 24501cae (AMD cimx/sb800: Initially
enable all GPP ports).

Change-Id: I5ac263ee088d36a7f7a2d03c1454ed647faa7147
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12190
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29 17:06:36 +01:00
Martin Roth eabce729a7 amd/sb700: clean up recommended changes
This patch addresses changes requested to commit 85c39a4c
(southbridge/amd/sb700: Add Suspend to RAM (S3) support)

- remove unused/commented out code
- remove unnecessary guards around acpi_get_sleep_type()

Change-Id: I2878e038d2f9f8d182615e1f4a75ddce5c45d5f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
2015-10-29 17:05:32 +01:00
Martin Roth bcaaad1c55 lint: Add Kconfig / Kconfig symbol lint tool
This is a tool to help identify issues in coreboot's Kconfig structure
and in how the Kconfig symbols are used in the coreboot codebase.

It identifies a number of issues:
- #ifdef used on Kconfig symbol of type bool, hex, or int.  These are
always defined.
- #define CONFIG_ in the coreboot code - these should be reserved
for Kconfig symbols.
- Redefinition of Kconfig symbols in the code.
- Use of IS_ENABLED() on non-bool kconfig symbols.
- Use of IS_ENABLED() on values that are not kconfig symbols.
- Attempts to find default values that will not set anything
because of earlier default settings.  This needs to be expanded
significantly.
- Kconfig expressions using symbols which are not defined.
- Kconfig symbols that are defined but not used anywhere in the
Kconfig structure or coreboot code.
- Kconfig keywords used incorrectly.
- Whitespace issues
- Kconfig 'source' keyword issues
-- sourcing non-existant directories
-- sourcing Kconfig files multiple times
-- sourcing non-existent files
-- Kconfig files in the codebase that are never sourced

Additionally, it can be used to help debug the Kconfig tree
by putting all the files together into a single file with
their source locations listed.

Run from the coreboot directory:
util/lint/kconfig_lint

Change-Id: Ia53b366461698d949f17502e99265c1f3f3b1443
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12088
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-29 17:05:08 +01:00
Aaron Durbin 694fd13390 cbfstool: extract rmodules as ELFs properly
With the previous ELF stage extract support the resulting
ELF files wouldn't handle rmodules correctly in that the
rmodule header as well as the relocations were a part of
the program proper. Instead, try an initial pass at
converting the stage as if it was an rmodule first. If it
doesn't work fall back on the normal ELF extraction.

TEST=Pulled an rmodule out of Chrome OS shellball. Manually
     matched up the metadata and relocations.

Change-Id: Iaf222f92d145116ca4dfaa955fb7278e583161f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12222
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-29 17:01:03 +01:00
Aaron Durbin cedcb882c1 cbfstool: add ELF symbol, relocation, and string table support
In order to convert rmodules back into ELF files one needs
to add in the relocations so they can be converted back to
rmodules. Because of that requirement symbol tables need
to be present because the relocations reference the symbols.
Additionally, symbol tables reference a string table for the
symbol names. Provide the necessary support for adding all
of those things to an ELF writer.

TEST=Extracted rmodule from a cbfs and compared with the
     source ELF file. Confirmed relocations and code sizes
     are correct.

Change-Id: I07e87a30b3371ddedabcfc682046e3db8c956ff2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12221
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-29 17:00:47 +01:00
Aaron Durbin 8e982eabfa cbfstool: merge consecutive elf sections in program segments
Instead of creating a loadable segment for each section with
SHF_ALLOC flag merge those sections into a single program
segment. This makes  more tidy readelf, but it also allows
one to extract an rmodule into an ELF and turn it back into
an rmodule.

TEST=Extracted both regular stages and rmodule stages. Compared
     against original ELF files prior to cbfs insert.

Change-Id: I0a600d2e9db5ee6c11278d8ad673caab1af6c759
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12220
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-29 17:00:38 +01:00
Aaron Durbin 5a1e85c405 cbfstool: create ELF files when extracting stages
Instead of dumping the raw stage data when cbfstool
extract is used on stage create an equivalent ELF file.
Because there isn't a lot of information within a stage
file only a rudimentary ELF can be created.

Note: this will break Chrome OS' current usage of extract
since the file is no longer a cbfs_stage. It's an ELF file.

TEST=Extracted romstage from rom.

Change-Id: I8d24a7fa4c5717e4bbba5963139d0d9af4ef8f52
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12219
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-29 17:00:24 +01:00
Aaron Durbin 4f930c9649 cbfstool: add ELF header initialization helper
In order for one to extract ELF files from cbfs it's
helpful to have common code which creates a default
executable ELF header for the provided constraints.

BUG=None
TEST=With follow up patch am able to extract out romstage
     as an ELF file.

Change-Id: Ib8f2456f41b79c6c0430861e33e8b909725013f1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12218
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-29 17:00:12 +01:00
Aaron Durbin 1762502929 cbfstool: add optional -m ARCH to extract
In order to prepare allowing for one to extract a stage
into an ELF file provide an optional -m ARCH option. This
allows one to indicate to cbfstool what architecture type
the ELF file should be in.

Longer term each stage and payload will have an attribute
associated with it which indicates the attributes of
the executable.

Change-Id: Id190c9719908afa85d5a3b2404ff818009eabb4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-29 16:59:54 +01:00
Timothy Pearson 3fcb11478f mainboard/asus/kgpe-d16: Properly configure SR5690 southbridge PIKE slot
Change-Id: I2f1373905ffd6460ac3c7c21738e2e2a9aa2e463
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11992
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-29 15:57:28 +01:00
Timothy Pearson cdc526e582 southbridge/nvidia/ck804: Fix boot hang on ASUS KFSN4-DRE w/ K8 CPU
Change-Id: Ie4b74f6d63c323ca499a6890defe9b8afe83ea96
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12209
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29 15:54:16 +01:00
Felix Held 8e1f020cee pcengines/apu1: adapt comments in devicetree to board
Change-Id: I09d2449af9c1562f4f3d5af1e8764b82b6550007
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12223
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-10-29 15:46:31 +01:00
Timothy Pearson 1d941068d8 northbridge/amd/amdk8: Improve DIMM detection debugging
Change-Id: I93534082d379369352e367c9c24b213513a543b2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12211
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-29 15:39:30 +01:00
Timothy Pearson d4bbfe863b mainboard: Convert #ifdef to IS_ENABLED in get_bus_conf.c
Change-Id: I254e9e9e65519edcf4d3f1ecc385af16d18c2367
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12208
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29 15:38:12 +01:00
Patrick Georgi ce2564ac51 smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG
This mitigates the Memory Sinkhole issue (described on
https://github.com/xoreaxeaxeax/sinkhole) by checking for the issue and
crashing the system explicitly if LAPIC overlaps ASEG.
This needs to happen without a data access (only code fetches) because
data accesses could be tampered with.

Don't try to recover because, if somebody tried to do shenanigans like
these, we have to expect more.
Sandybridge is safe because it does the same test in hardware, and
crashes. Newer chipsets presumably do the same.

This needs to be extended to deal with overlapping TSEG as well.

Change-Id: I508c0b10ab88779da81d18a94b08dcfeca6f5a6f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11519
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-10-29 10:27:00 +01:00
Furquan Shaikh 6fecb7106e vboot2: Fix flows for TPM_E_MUST_REBOOT
While migrating from vboot1 to vboot2, the tpm_init was moved out of
vboot library and implemented in coreboot. However, while doing this,
the initial factory flow was missed.

We need to ensure following flow for tpm_init:
1. Perform tpm_init
2. If tpm_init fails, set secdata_context flag to indicate to vboot
   that tpm needs reboot.
3. Call vb2_api_phase1
4. If vb2_api_phase1 returns error code saying boot into recovery,
   continue booting into recovery. For all other error codes, save
   context if required and reboot.

[pg: everything but step 2 was already done, so this upstream commit is
quite minimal]

CQ-DEPEND=CL:300572
BUG=chrome-os-partner:45462
BRANCH=None
TEST=Verified behavior on smaug. Steps to test:
1. Reboot into recovery
2. tpmc clear
3. Reboot device

Expected Behavior: Device should reboot after Enabling TPM. Should not
enter recovery

Confirmed that the device behaves as expected.

Change-Id: I72f08d583b744bd77accadd06958c61ade298dfb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 85ac93137f3cfb28668dcfa18dfc773bf910d44e
Original-Change-Id: I38ab9b9d6c2a718ccc8641377508ffc93fef2ba1
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/300570
Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12205
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-10-28 22:28:28 +01:00
Patrick Georgi 5dba15c180 3rdparty/vboot: update to current master
Change-Id: Idc300472f8d8821dd362d6dd075150f285f1d09b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12207
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-10-28 22:28:16 +01:00
Duncan Laurie f012f1276e google/glados: Set the type-c flex port to max USB2 settings
Change the tuning setting for the type-c port that is over
the flex cable to use the max possible drive strength.

Also fix up the comments to indicate what Type-c port goes
where instead of just referring to them by number.

BUG=chrome-os-partner:45367
BRANCH=none
TEST=build and boot on glados

Change-Id: Iebcffc9ab95d56289258017248c273090c88bb06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 824ca87c4bf556d493dc8cdec561f37ab135cd2d
Original-Change-Id: I081623bbb1b0f39f1569b9f5cf7933abefe202b3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309010
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12204
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28 22:28:03 +01:00
Duncan Laurie 823259332c intel/skylake: Add USB2 port config for max settings
Add a new USB2_PORT_MAX with the max possible settings
(56mV) for the TX and Pre-emphasis bias values.  Also fix
the settings for the detachable tablet config to match the
skylake HSIO tuning guide as it was incorrect before.

BUG=chrome-os-partner:45367
BRANCH=none
TEST=build and boot on glados

Change-Id: Id9ccc683fe92c962095347e0d1a0afeb082c821f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e5d56831e75f98a3c75ed333e4b79b1a37f14792
Original-Change-Id: Ia2e3e93236f1463201f83a1cae28349de2836110
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/308729
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12203
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28 22:27:54 +01:00
Duncan Laurie ba5487acf4 google/chell: Set DPTF critical temperature to 99C
If we boot without a heatsink then DPTF may power off the system when
it starts if the CPU temp is >90C.  Since TJmax is 100C set the
critical threshold to just below that value.

Also remove the active thresholds as chell does not have a fan.
This will have DPTF use the default values but without the DPTF active
policy it shouldn't get used.

BUG=chrome-os-partner:46694
BRANCH=none
TEST=build and boot on chell w/o a heatsink

Change-Id: Id9e8f2c547468db8ad0edaf6c362a9a9bb5b95a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23d9117d5d7a4b44fc2298352eba133747f8e246
Original-Change-Id: Ib8e074098e3956efeed0f9b7f8b16652658db374
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/308728
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12202
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28 22:27:45 +01:00
david f372fb5529 google/lars: Add new mainboard
This is based on kunimitsu with minor changes:
- update GPIOs based on schematic
- update SPD data for memory config
- disable ALS

BUG=None
TEST=emerge-lars coreboot

Change-Id: Id1c9edfe3cc665e90683344f1662de2e65caf766
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3201aa573a77fcad3b6b1335d23eb4c2a09c1708
Original-Change-Id: Ifae446e4668569b6100b29bc1f52b0fea1df2952
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308283
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/12201
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28 22:27:36 +01:00
david ad038c1a14 google/lars: Copy from intel/kunimitsu
Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12200
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28 22:27:24 +01:00
Daisuke Nojiri 6ce7459d67 vboot: check vb2_shared_data flags for manual recovery
vboot handoff should look at flags in struct vb2_shared_data when
translating flags to VBSD_BOOT_REC_SWITCH_ON because
VBSD_BOOT_REC_SWITCH_ON is supposed to indicate whether manual recovery was
triggered or not while vb2_sd->recovery_reason will be able to provide
that information only in some cases after CL:307586 is checked in.

For example, this fixes a recovery loop problem: Without this fix,
vb2_sd->recovery_reason won't be set to VB2_RECOVERY_RO_MANUAL when user
hits esc+refresh+power at 'broken' screen. In the next boot,
recovery_reason will be set to whatever reason which caused 'broken'
screen. So, if we check recovery_reason == VB2_RECOVERY_RO_MANUAL, we
won't set vb_sd->flags to VBSD_BOOT_REC_SWITCH_ON. That'll cause a
recovery loop because VbBootRecovery traps us again in the 'broken'
screen after not seeing VBSD_BOOT_REC_SWITCH_ON.

BUG=chromium:501060
BRANCH=tot
TEST=test_that -b veyron_jerry suite:faft_bios

Change-Id: I69a50c71d93ab311c1f7d4cfcd7d454ca1189586
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d9679b02f6d21ed903bb02e107badb0fbf7da46c
Original-Change-Id: I3da642ff2d05c097d10db303fc8ab3358e10a5c7
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/307946
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/12199
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28 22:26:23 +01:00
Daisuke Nojiri 2ccb280f51 cbfs: read cbfs offset and size from sysinfo
This change allows libpayload to read cbfs offset and size from sysinfo.
Legacy way of locating cbfs reagion is still supported in case sysinfo
doesn't store the offset and the size.

BUG=none
BRANCH=master
TEST=tested on samus and smaug

Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c
Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296993
Original-Commit-Ready: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11557
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28 22:26:17 +01:00
Martin Roth 158d00148f cpu/intel/fsp_model_206ax: Load microcode in coreboot
Intel's FSP 1.0 platforms are moving back to loading microcode in
coreboot instead of in the FSP.  Update the Ivy Bridge chips to
be compatible.

Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12196
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-28 19:22:04 +01:00
Patrick Georgi 64d04806f9 lint: don't check for whitespace in jpeg images
Change-Id: I0e1bbb198be6512e9f696c3dddca7f65436e6f5b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/12182
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-10-28 19:15:25 +01:00
Patrick Georgi 246179a808 jpeg: add jpeg_fetch_size()
This aids the fuzzer test case.

Change-Id: Ic7d43b76cf5660e085e7b3b13499de0358c13197
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/12181
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-10-28 19:15:17 +01:00
Jason A. Donenfeld a5c5db37ee cbgfx: Fix spelling of calculate_position()
Change-Id: Ib0dc14b197091450596ad01a924539b0e69acd68
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-on: http://review.coreboot.org/12216
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-28 17:09:59 +01:00
Timothy Pearson 53538be49d mainboard/asus/kgpe-d16: Add initial support for the KGPE-D16
As of this commit S3 suspend does not work on any K10 boards,
including this board.

Change-Id: Idd3971422fb2473bff7c60fe8d8161d6e20808ed
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11946
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-28 01:22:10 +01:00
Timothy Pearson 85c39a4ce5 southbridge/amd/sb700: Add Suspend to RAM (S3) support
Change-Id: Ic643e31b721f11a90d8fb5f8c8f8a3b7892c0d73
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11949
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 20:16:29 +01:00
Aaron Durbin 539aed0646 cbfstool: decompress stage files on extraction
In order to actually do something useful with the
resulting file after being extracted decompress stage
files' content. That way one can interrogate the
resulting file w/o having to decompress on the fly.

Note: This change will cause an unexpected change to
Chrome OS devices which package up individual stage
files in the RW slots w/o using cbfs. The result will
be that compressed stages are now decompressed.

Longer term is to turn these files into proper ELF
files on the way out.

Change-Id: I373ecc7b924ea21af8d891a8cb8f01fd64467360
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12174
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-27 17:52:57 +01:00
Paul Menzel 662380f157 device: Stop and output time in `scan_bus()`
Output how long it took to scan a bus.

Note, that the function `scan_bus()` is called recursively.

Change-Id: I6335e10db783f092ea18d3a1c79f93135bee5826
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12103
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 17:14:11 +01:00
Patrick Georgi 990ae70698 libpayload/libcbgfx: Add license headers
Change-Id: I09a9d9eef9d8fe45cdd4d68d29b8d662fe5956e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12164
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-27 16:49:10 +01:00
Paul Menzel be70646ccc include/timer.h: Guard `timer_monotonic_get()` calls by `CONFIG_HAVE_MONOTONIC_TIMER`
Some platforms do not have `timer_monotonic_get()` implemented. So only
call `timer_monotonic_get()` if `CONFIG_HAVE_MONOTONIC_TIMER` is
selected and set the times to 0 otherwise.

Change-Id: If9cba4c0c17a7011aa357079d8fdd0aa47ad1b66
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12105
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 16:07:50 +01:00
Daisuke Nojiri dcc63b6cb7 cbgfx: remove load_bitmap
load_bitmap is no longer needed.

BUG=none
BRANCH=master
TEST=Tested on Samus
CQ-DEPEND=CL:305589

Change-Id: I4e598ade20a5d49850f9ad0f13681ea5d16cd8c7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 125bbc98195cbb8378ba0e4c7fece85ffca4cdfa
Original-Change-Id: I64d685f7a6367b03455ae2a206b9936613614a24
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/305517
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11930
Tested-by: build bot (Jenkins)
2015-10-27 15:22:53 +01:00
Daisuke Nojiri 20b7907041 cbgfx: add get_image_dimension
get_image_dimension returns the width or height of the image projected on
canvas.

This is necessary for example when two images of different lengths have to
be placed side by side in the center of the canvas and the widths of the
images must be adjusted according to the height.

BUG=chromium:502066
BRANCH=tot
TEST=Tested on Samus

Change-Id: I119c83891f48046e888b6b526e63348e74f8b77c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d1a97f0492eb02f906feb5b879b7b43518dfa4d7
Original-Change-Id: Ie13f7994d639ea1556f73690b6b6b413ae64223c
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304113
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11929
Tested-by: build bot (Jenkins)
2015-10-27 15:22:41 +01:00
Daisuke Nojiri 9aed1465d7 cbgfx: make the code more descriptive
This change makes the code in graphics.c more descriptive and readable.
Especially, it makes expressions for scale calculation look what they
are meant to do. It also includes:

- Rename variables (struct fraction, dim_org, etc.) for more consistency
- Add more input validation (div-by-zero, etc.)

BUG=chromium:502066
BRANCH=master
TEST=Tested on Samus
CQ-DEPEND=CL:304860

Change-Id: I2694912bb7b6017d5655de2fd655b95432addb22
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0863dc3ee925d3a05c83c66397b19a57f5478ef3
Original-Change-Id: Id8e349b8e09082fb84c3e1a984617f916e16c518
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304861
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11928
Tested-by: build bot (Jenkins)
2015-10-27 15:22:33 +01:00
Daisuke Nojiri a11e3ff160 cbgfx: add pivot option to draw_bitmap
This change adds 'pivot' option to draw_bitmap. It controls the point of the
image based on which the image is positioned. For example, if a pivot is set
to the center of the image horizontally and vertically, the image is
positioned using pos_rel as the center of the image.

This feature is necessary, for example, to place a text image in the center
of the screen because each image has a different width depending on the
language.

This change also makes draw_bitmap accept both horizontal and vertical size.
If either of them is zero, the other non-zero value is used to derive the
size to keep the aspect ratio.

Specifying the height is necessary to keep font sizes the same when drawing
text images of different lengths.

draw_bitmap_direct is a variant of draw_bitmap and it draws an image using
a native coordinate and the original size (as opposed to the location and
the size relative to the canvas).

CL:303074 has real use cases.

BUG=none
BRANCH=tot
TEST=Tested on Samus

Change-Id: I5fde69fcb5cc9dc53e827dd9fcf001a0a32748d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 82a0a8b60808410652552ed3a888937724111584
Original-Change-Id: I0b0d9113ebecf14e8c70de7a3562b215f69f2d4c
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302855
Reviewed-on: http://review.coreboot.org/11927
Tested-by: build bot (Jenkins)
2015-10-27 15:22:24 +01:00
Daisuke Nojiri f86515244a cbgfx: use bilinear interpolation to scale bitmap
This change replaces the current scaling algorithm (nearest neighbor) used
for bitmap rendering with the bilinear interpolation, which has much better
reproduction.

BUG=none
BRANCH=tot
TEST=Tested on Samus

Change-Id: I02520883debb7db40ffc19d4480244e0acabc818
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 764b383c1763a022728f2b2d9fb90e27c9e32e94
Original-Change-Id: I0ddd184343428904d04d8a76fe18a885529c7d3d
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302195
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/11926
Tested-by: build bot (Jenkins)
2015-10-27 15:22:16 +01:00
Daisuke Nojiri bed16d9706 cbgfx: add load_bitmap
This change adds load_bitmap API, which loads a bitmap file from cbfs
and returns a pointer to the image data.

BUG=none
BRANCH=tot
TEST=Tested on Samus

Change-Id: I7d7874f6f68c414dc877a012ad96c393e42dc35e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9d33e713a0cf6bd1365418dad989e47e86db01e4
Original-Change-Id: Idbf9682c2fa9df3f0bd296ca47edd02cd09cfd01
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302194
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/11925
Tested-by: build bot (Jenkins)
2015-10-27 15:22:10 +01:00
Daisuke Nojiri fed269b1c4 cbgfx: add clear_screen
clear_screen clears the screen with the specified color.

BUG=none
BRANCH=tot
TEST=Tested on Samus

Change-Id: I45e61c67485dbdbe15e2b602718232bc6382ad00
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1ab04e2cc8d3c3e36e4eb41d9e7b0fdc25595200
Original-Change-Id: I1b3890b9e8ca52e796f417b5f41d4fa02a97a255
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/301451
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/11924
Tested-by: build bot (Jenkins)
2015-10-27 15:22:00 +01:00
Daisuke Nojiri dd49eccb50 cbgfx: allow draw_bitmap to render outside canvas
This change allows draw_bitmap to draw an image outside the canvas
with the original size if the scale parameter is zero. This is used
for example when drawing a splash screen which has to be positioned
at a pixel perfect location.

BUG=none
BRANCH=master
TEST=Draw pictures and boxes on Samus and Ryu

Change-Id: Ia2d8799184d1aa192e2c50850e248bee8f234006
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 45d4717fe5c3e3554bd79b63ade490d88cf00bbe
Original-Change-Id: I48aa21122cfc2ee43bcb1b8f87b00c66abdc230e
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295961
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11923
Tested-by: build bot (Jenkins)
2015-10-27 15:21:53 +01:00
Daisuke Nojiri 09ad206cda cbgfx: add draw_bitmap
draw_bitmap renders a bitmap image on screen with position and sizes
scaled relative to the screen. images are scaled up or down by nearest
neighbor interpolation.

BUG=chrome-os-partner:43444
BRANCH=tot
TEST=drew bitmap images on Samus

Change-Id: Ib599acc85b25626a6aed1fa9884ecd8e169bb860
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c910c9cdb7efc53aace067bd081aeefc07556811
Original-Reviewed-on: https://chromium-review.googlesource.com/290302
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Change-Id: Ib599acc85b25626a6aed1fa9884ecd8e169bb860
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295532
Reviewed-on: http://review.coreboot.org/11584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:21:42 +01:00
Daisuke Nojiri 3f66398ef8 cbgfx: coreboot graphics library
This change introduces cbgfx, a graphics library, which provides APIs for
drawing basic shapes, texts, graphic data, etc. on a screen.

BUG=chrome-os-partner:43444
BRANCH=tot
TEST=Drew boxes by draw command of depthcharge cli on Samus

Change-Id: I6019e5998e65dca3ab4785a90669b5db02463d2e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 5b3ebce8eae91be742e4f977d3407d24e1537580
Original-Reviewed-on: https://chromium-review.googlesource.com/290301
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Change-Id: I10db27715cb907bdc451a33ed99d257e3af241b7
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291065
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11408
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:21:31 +01:00
Duncan Laurie fe86666913 intel/skylake: Clean up USB configuration in devicetree
Instead of having many different arrays for USB configuration,
with each array containing one bit of information, have one
array containing all the information for each port.

This way we can put the basic tuning parameters into a
structure and then define structures for the basic supported
configurations.

The existing port definitions are taken from the Skylake HSIO
tuning guide.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados, verify USB functionality in
all ports.

Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506
Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/306734
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12163
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:20:36 +01:00
Yong Zhi 4f1fe47178 intel/kunimitsu: Add device properties for Nuvoton code
Add default properties for NAU8825 codec
Change jack detecion irq to level to match the
codec driver

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Build and Boot Kunimitsu board with this patch
Verify Audio jack detection IRQ working

Change-Id: Iaab7a7bfbab30fa0914e56477f7c6a93717b4518
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58c45538ea6a85724f9ab1837e5cf0971611a1f8
Original-Change-Id: I11466b8fd64b768e1e826639ba37bd6e00810370
Original-Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303760
Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com>
Original-Tested-by: Yang Fang <yang.a.fang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12162
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:20:27 +01:00