Instead of having the mainboards duplicate logic surrounding
LPDDR4 initialization provide helpers to do the heavy lifting.
It also handles the quirks of the FSP configuration which allows
the mainboard porting to focus on the schematic/design.
Change-Id: I686eb3097c33399a3b94af89237f7fe1b2d34c2f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14790
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
PCI device ID of this mini-PCI-e WLAN card is 8086:088e.
With this card inserted on pcengines/apu1 mini-PCI-e slot J17,
system halts late in ramstage, in agesawrapper AMD_INIT_MID.
Offending operation is enabling PCIe ASPM L0s and L1 for the card.
That is, writing PCIe capability block Link Control [1:0] = 11b
in the card's configuration space. AGESA already has a blacklist
for the purpose of masking such unstable ASPM implementations.
Change-Id: I9623699c4ee68e5cdc244b87faf92303b01c4823
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/8496
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the option is not provided, ssh uses the default port for the host,
which is usually 22, but may be overridden in the user's SSH
configuration.
Change-Id: I303e9aeae16bd73a96c5e6d54f8e39482613db28
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14522
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
In some configurations, "git push <remote>" (without a branch name)
refuses to do anything.
Change-Id: I23a401b39dd851e9723676586c7f29afa111b49d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14539
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
In order for apollolake mainboards to utilize the common GPIO API
it actually needs to be implemented.
Change-Id: I41de8d5d9f3c39e7e796eae73b01cb29e9c01347
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14797
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to allow using the same C source to be compiled
for multiple stages (with #if/#endif guards) one needs the
necessary function delcarations. Therefore, remove the
guards.
Change-Id: Iea94d456451c5d3db8b8b339e81163b3b3fed3ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14796
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
- manpage
- usage message
- new warning message if -S is used on an unsupported chipset
Change-Id: I1acaa5f4232b65244ec00fd22ec7460d9cc387f1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14624
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Not used as we link AGESA into same romstage and ramstage ELF.
Change-Id: Ia427b9c0cc88b870de75df14bba4ca337a28adff
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14395
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ACPI BAR (BAR2 - offset 0x20) is not PCI compliant. That means
that probing may not work. In that case, a resource still needs to be
created for the BAR.
BONUS: We now avoid the need to declare the MMIO resources as fixed.
Change-Id: I52fd2d2718ac8013067aaa450c5eb31e00738ab9
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14634
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to
be done in platform code.
Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14764
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The old code only checked for an RW_MRC_CACHE region when
CONFIG_CHROMEOS was selected. This assumption is not necessarily true,
as one can have FMAP without a CHROMEOS build. As a result, always
search FMAP first before falling back on CBFS for locating the MRC
cache region.
The old logic where CHROMEOS builds would fail when RW_MRC_CACHE was
not found is preserved, such that behavior does not change.
Change-Id: I3596ef3235eff661af055968ea641f3e9671cdcd
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14757
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When SOC_UART_DEBUG was not set, the boot would hang somwhere in
ramstage, as evidenced by POST codes reported from the EC. This was
traced to the .set_resources and .enable_resources members of the UART
PCI driver being set to NOOP.
Although the exact mechanism of failure is not known, this change
eliminates the hang.
Change-Id: Ic2f3d56a964ec890ebfa1e1a7770f1ae2eb22281
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14771
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for Elan touchscreen on I2C3 for amenia
BUG=None
TEST=Boot to Chromium OS and verify if touchscreen is working.
Change-Id: Ic75bef0e5878bd5b8c0d727400679663d9f591e3
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/14768
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to provide other stages access to the ioport range
required by the ChromeEC provide google_chromeec_ioport_range()
function to fill in the details. Currently, the ioport range is
only consumed by the LPC implemenation. Also allow ec_lpc.c to be built
for the bootblock stage.
Change-Id: I6c181b42e80e71fe07e8fa90df783107287f16ad
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14769
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however
the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define.
Those 2 values are not consistent. Therefore, remove the Kconfig
variable and defer to the #define generated by fmdtool.
Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14765
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Remove the phrase "which accompanies this distribution" from the license.
Re-format the license to fit in 80 columns.
TEST=Build and run on Galileo Gen2
Change-Id: I8d893cf1270b95b27eab7142b276ebfce24ec2ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14774
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
FSP 2.0 uses the same relocate logic as FSP 1.1. Thus, rename
fsp1_1_relocate to more generic fsp_component_relocate that can be
used by cbfstool to relocate either FSP 1.1 or FSP 2.0
components. Allow FSP1.1 driver to still call fsp1_1_relocate which
acts as a wrapper for fsp_component_relocate.
Change-Id: I14a6efde4d86a340663422aff5ee82175362d1b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14749
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently, convert_fsp assumes that the component is always XIP. This
is no longer true with FSP 2.0 and Apollolake platform. Thus, add the
option -y|--xip for FSP which will allow the caller to mention whether
the FSP component being added is XIP or not. Add this option to
Makefiles of current FSP drivers (fsp1_0 and fsp1_1).
Change-Id: I1e41d0902bb32afaf116bb457dd9265a5bcd8779
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The origin of UART config is less interesting than having the config be
correct.
Change-Id: I834e3a54105a8fd7d62f388e4a9ad0992ecec807
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14767
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
The code needs to know what kind of part the SoC is, but the question
was weirdly phrased and also exposed to the user (instead of being a
silent "select" to do in a board).
Change-Id: I0344c528d86ac047fc49ccff9e149865bbd4b481
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14766
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
BUG=none
BRANCH=none
TEST=compiled
Change-Id: I125585e33783a39194bb12b2dd746bb968da5fee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e6f986e57bc1ce341e1b0ae6a419d4bbe0f169aa
Original-Change-Id: Ife4cde2318e007a76c978973c13bbce583d082a8
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/343556
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Rename Ipq806xLcc* to IpqLcc*.
Change-Id: Ib235c1cdb36bb007a673133f59026863990e1a6f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Increase the HEAP size to handle large vpd data.
BUG=chrome-os-partner:50499
TEST=board with vpd data no longer showing out of memory error
BRANCH=none
Change-Id: Ia0793a626c3500c3469c608bae987ae15a176016
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12090652d2b70ec553a4f59fe9917a1b3b204579
Original-Change-Id: I1ead4c104b27cf678c68132b0ab08e32c15790b2
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/340267
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14682
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Clear the crash dump cookie set by SBL to indicate that
it is a normal reset.
Inform DDR image of the entrypoint for SDI image to be
preserved in OCIMEM which will be needed during watchdog
resets.
BUG=chrome-os-partner:49249
TEST=DDR image is able to fetch the entry point address
BRANCH=none
Change-Id: I3e6e4a108585bb257e3ad02956c420acbcb2554e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd726256a5ae89672810b57e1d2a7a9287f60627
Original-Change-Id: Id6e09516209f47c3ea8fa3d8d90440789b395660
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333321
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14679
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Able to talk to the TPM device and the commands
seem to succeed.
BUG=chrome-os-partner:49249 chrome-os-partner:49250
TEST=All commands to the TPM succeed
BRANCH=none
Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd
Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333314
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
squashed:
soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI
- Enable BLSP SPI driver for ipq40xx
- supports only FIFO mode
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9
Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333303
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Without monotonic timer support, timer related APIs like
timer_monotonic_get etc. are optimized out by the compiler. This
results in timed loops to become indefinite loops
stopwatch_init_msecs_expire(...);
do {
something();
} while (!stopwatch_expired(...));
In our specific case, loops sampling the recovery/wipeout button
in src/mainboard/google/gale/chromeos.c:get_switch_state() turned
into infinite loops and the boot didn't proceed.
BUG=chrome-os-partner:49249
TEST=Confirmed that the loop breaks per the specified timeout
using the minicom's console log time stamps
[2016-04-11 12:34:37] recovery button pressed
[2016-04-11 12:34:45] wipeout requested, checking recovery
[2016-04-11 12:34:53] recovery requested
BRANCH=none
Change-Id: I7ed2616c50ebb28b43ad769d3105f7d4e31b1114
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e00f888570b577849cb526220ffe6f22fe9d2ece
Original-Change-Id: Ic0b800558ebce482da6321c30dbf732080b82941
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/339873
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Kan Yan <kyan@google.com>
Reviewed-on: https://review.coreboot.org/14673
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
DDR binary runs from here
BUG=chrome-os-partner:49249
TEST=Boots and DDR seems to be usable
BRANCH=none
Change-Id: I6111dddcabf05e5cb84ee9ebcc1803addb1e91cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7baf2079845964a150f51d558b396a1a9b0dc0a3
Original-Change-Id: I1d7230b229db3abfb73e6d8f9ca085650e6abec8
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333313
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14671
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This file had the memory regions applicable to ipq806x.
Update the regions as applicable to ipq40xx.
BUG=chrome-os-partner:49249
TEST=Able to boot on DK04 board
BRANCH=none
Change-Id: I0d782eb70fd62c6bf92f9fac39d2e42e9af82012
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e6a088c2666cf5be52358bb4271b45cb65d11f7c
Original-Change-Id: I4fb3ca7fb168813d8871bfb87d475fd09d1a9d97
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333310
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Change-Id: I7c58fe7dc0132e8c01163fc049217f07081c658a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d746b667e309fd8eec62cf84e4ea4006ab2984f0
Original-Change-Id: Idcb3189a812e75815eb15a61c1de273b5e218875
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333305
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14669
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Set SAGV to 2 (Fixed High) so that MMA test would
stress memory at high freq point. MMA tests does not
support stressing memory at both high and low points.
BRANCH=glados
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu and ran MMA tests.
Change-Id: I0b2f6cf9955076f6146b957c4d40fe24e6c3f0e7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4b16b756d9a74c9111c78fce848b059daee65669
Original-Change-Id: I4c4a59407844e1986fa2cf3a0035aff1d8529cf9
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339002
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-(cherry picked from commit c43d9880fe4efd1e1bb853d35140424fb7dd7e99)
Original-Reviewed-on: https://chromium-review.googlesource.com/338847
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/14697
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(1) Added following new function.
cbfs_locate_file_in_region - to locate (and mmap) a file in a flash
region
This function is used to look for MMA blobs in "COREBOOT" cbfs region
(2) mma_setup_test.sh would write to "COREBOOT" region.
(3) changes in mma_automated_test.sh. Few MMA tests need system to
be COLD rebooted before test can start. mma_automated_test.sh would
do COLD reboot after each test, and so i would sync the filesystem
before doing COLD reboot.
BRANCH=none
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu (FAB4). Able to locate MMA files in CBFS
Not tested on Glados.
Change-Id: I8338a46d8591d16183e51917782f052fa78c4167
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1e418dfffd8a7fe590f9db771d2f0b01a44afbb4
Original-Change-Id: I402f84f5c46720710704dfd32b9319c73c412e47
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331682
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/14125
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
mma_automated_test.sh takes a config file (/usr/local/mma/tests) as
input and executes all tests mentioned in the config file.
format of the config file is one or more lines mentioned below.
<MMA test name> <MMA test param> <#count>
e.g. consider following config file.
Margin1D.efi Margin1DRxVrefConfig.bin 4
RMT.efi RMTConfig.bin 1
MarginMapper.efi ScoreTxVref-TxDqDelayConfigCh1.bin 2
Margin2D.efi Margin2D_Cmd_Ch0_D1_R0_Config.bin 3
This will execute Margin1D.efi MMA test 4 times with
Margin1DRxVrefConfig.bin param and results will be stored
in DUT under /usr/local/mma/results_<date-time-stamp>
with Margin1D_Margin1DRxVrefConfig_1.bin to
Margin1D_Margin1DRxVrefConfig_4.bin name. Subsequently all tests
will be executed and results will be stored.
/etc/init/mma.conf invokes mma_automated_test.sh when DUT
starts. And if valid test config is preset at /usr/local/mma/tests,
mma_automated_test.sh will continue executing the tests. Each time
DUT will be rebooted and next test in sequence will be executed.
Overall follow these steps to start MMA.
(1) create /usr/local/mma/tests file with the syntax mentioned above.
(2) either reboot the DUT (mma.conf will be called at each boot time,
which would run the mma_automated_test.sh) or execute "start mma"
command (to save a reboot cycle.)
(3) all test results can be found under
/usr/local/mma/results_<date-time-stamp> where <date-time-stamp> is
YY_MM_DD_HH_mm format (YEAR_MONTH_DAY_HOUR_MINUTE) when you started
the mma tests.
BRANCH=none
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu (FAB3). MMA automation tests executes
and results get saved.
Change-Id: I6805fdb95b7ff919f9c8e967b748e4893a3f9889
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 68c0a531ba3fc335b92b17002e75412195b778c4
Original-Change-Id: I92db7ca47e1e3e581c3fbb413f11e2c3e6d19b6b
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313180
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is stale code from ipq806x, n/a for ipq40xx.
Hence removing it.
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Change-Id: I2ac73677f77d4bfbc70f56c73a661cc2c22dd384
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f9796588648bc477f118282aad89037f0577f23
Original-Change-Id: I8bcf928ee23ac24a21b0e633e207354ea9fa0511
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333299
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14664
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Implement reset using PSHOLD and remove watchdog
based reset not needed for ipx40xx.
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Change-Id: Ic2fa0e7676604f36a99750b4bda53195199ebc69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 65c8b9dd633f0d402cad7d609563c8aac9bf5115
Original-Change-Id: I8f0ea3c1b71e86a7ca733965ecbec6954a52f6e3
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333298
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14750
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Original-Commit-Id: 35c0e6046899dc1af03736ae9fa77f9eeec7f668
Original-Change-Id: I681e92fa673c1d3aee2974a7bba5074e2bfd6e02
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333297
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
squashed:
soc/qualcomm/ipq40xx: Enable UART on ipq40xx
- BLSP/UART Clock configuration
- GPIO Configuration
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Original-Commit-Id: 7bba1fc7f50e7aeb4e7b37f164e85771e53f47e6
Original-Change-Id: I474a0e97b24ac9b3f2cba599cd709b6801b08f91
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333300
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I5e31d036ee7ddcf72ed9739cef1f7f7d0ca6c427
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14667
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Aaron Durbin