Commit Graph

3115 Commits

Author SHA1 Message Date
Ed Swierk 83a965d2ef Implement GPIO configuration routines for the Intel 3100 southbridge,
allowing you to specify per-mainboard GPIO settings.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 21:57:12 +00:00
Jordan Crouse aa6e378c4e coreinfo: Add a module for browsing the boot LAR
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 20:43:15 +00:00
Jordan Crouse 681ec27e2c libpayload: Add LAR walking support
Add suport for walking LARs.  These try to emulate the f*
functions from POSIX, though they are obviously different
in their behavior.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 20:34:02 +00:00
Ed Swierk 35993a231e Fix a typo in lbtdump output (trivial).
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 19:21:18 +00:00
Jordan Crouse 193378698e coreinfo: Show the current time and date in the menu
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:15:31 +00:00
Jordan Crouse de7fc55920 We were in the risk of running out of space in the option menu at
the bottom of the screen - this turns the function keys into
categories and then list specific items as part of the category.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:03:16 +00:00
Jordan Crouse 7ce2666249 The previous commit had more in it then I wanted - so I am reverting
this and re-commiting so that the history and comments are correct.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:00:55 +00:00
Jordan Crouse 646ee3eae9 coreinfo: Move the rdtsc.h include into the #ifdef CONFIG_MODULE_CPUINFO
rdtsc.h shouldn't be included unless we really need it (and use it).
Trivial.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 21:32:52 +00:00
Marc Jones 9d9518ff54 cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a
pci_write_config8.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 16:56:47 +00:00
Myles Watson c314b2fcec This patch changes Config-lab.lb for qemu to use lzma like the other targets.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 15:17:43 +00:00
Aaron Lwe 2342f8b343 This patch adds pc keyboard init function call for qemu in v2 since some payloads assume
Coreboot initializes it.  Coreboot v3 already does it.

Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 15:02:22 +00:00
Jonathan A. Kollasch 4f9141758e Fix various issues on MSI MS-7135 board.
- W83627THF is strapped to 0x4e, not 0x2e
 - there's no device 9 on PCI-E x1 bus, it should be device 0
 - add mptable entries for AGR slot, based on info in user manual
 - enable floppy drive controller so that some legacy VGA ROMs will work

Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 13:26:32 +00:00
Ward Vandewege 33c57f8403 This patch changes the payload path for Config.lb; this board is supported by
buildrom and this bit was forgotten during r3092.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-05 20:50:58 +00:00
Peter Stuge 4934fc03cb flashrom: Add a tested bitmap field to the flash chip table.
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
8 bits out of 32 are in use now. No bits set means nothing has been tested.
For chips with at least one operation that is not tested or not working, the
user is asked to email a report to a special email adress so that the table
can be updated.

All chips are TEST_UNTESTED for now.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-03 04:34:37 +00:00
Ed Swierk a9a5f49d8f By default, the Intel 3100 LPC interface enables only I/O range 0x3f8
for both serial ports, making it challenging to use COM2 for the early
console.

Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-30 18:29:35 +00:00
Bari Ari e21f836e4e flashrom: Enable ROM decode range to 1MB for vt8237r
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-29 13:46:38 +00:00
Claus Gindhart b19973eb8b The generic jedec.c does not work for the ST M50FLW flash
devices, because they need an unlock command first.
For this reason, ST M50FLW support is moved to a
new HW support module, because any change in jedec.c
would bear the risk to cause problems with the already
supported devices.

It's already tested with ST M50FLW080A; the other
chips of this family i dont have available, so i couldnt
test it.

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28 17:51:09 +00:00
Peter Stuge 26e08b5abe flashrom: Handle NULL probe, erase and write function pointers in the
flashchips table. The read pointer was already checked properly.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28 14:47:30 +00:00
Jordan Crouse e2271430c5 libpayload: Add gettimeofday() and friends
Add a gettimeofday() implementation - it works pretty well, but it
drifts a little bit so its not very suitable for keeping time.  It
works best to track changes in time over small periods of time.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:11:02 +00:00
Jordan Crouse d772e1e7fe libpayload: Fix a small but aggressive bug in printf()
This was causing the returned counter value to be one more then it
should be when printing a single character.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:10:23 +00:00
Jordan Crouse 63f181f97c libpayload: Enable keyboard translation so that we can use scancode set 1
The qemu keyboard controller defaults to using scancode set 2, we use set 1.
Turn on the translate mode in the keyboard controller to force the issue.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:09:39 +00:00
Jordan Crouse 24a0404759 libpayload: Fix malloc allocation
Apparently the previous version worked on luck.  Fix the allocation
and add parens to better guide the compiler.  Also, halt() if 
the heap is poisoned (like by an overrun).  Finally, fix calloc()
so that it actually works.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:08:47 +00:00
Jordan Crouse c781584936 libpayload: Add the null terminator to the end of the duplicated string
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:07:39 +00:00
Marc Jones 20ce60c9aa Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb.
The FAM10 code takes up more space in the uncompressed "ROMCC" portion
of coreboot. Also, It is still growing as features are added.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 22:56:57 +00:00
Marc Jones 65e08040f9 Remove inline from FAM10 CPU initialization functions.
This doesn't save any space for me but it is the right thing to allow GCC to
optimize.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 21:34:25 +00:00
Aaron Lwe 7ca3ec2e5c Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 02:02:33 +00:00
Uwe Hermann 6fd385d154 Payload location fix for buildrom (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 00:38:41 +00:00
Marc Jones c1cbff217a Add CPUID processor name string support for Fam10 CPUs.
Peter did a nice job cleaning up my initial patch. Thanks!

Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Peter Stuge <peter@stuge.se>

Acked-by: Marc Jones <marc.jones@amd.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 20:03:13 +00:00
Marc Jones 403b89a14f On APs the ClLinesToNbDis was being left enabled from CAR setup.
Disabling it should help performance.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 19:49:59 +00:00
Nikolay Petukhov 202625e61f This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX)
is based on amd-lx800/cs5536.

Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 13:37:01 +00:00
Claus Gindhart 20ba8eb7ab Flash pages, which where excluded from updating using the exclude or the
layout option, as well as areas, whose flash contents already contain the
desired data, will be skipped.
These ensures absolute data security of critical areas (BIOS boot block), 
e.g. against a sudden power off or a CPU hangup during flashing. As a
nice side effect, it speeds up the flash process, if the BIOS to be flashed
is very similar to the version in flash. 

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 09:07:57 +00:00
Carl-Daniel Hailfinger a149131415 Same old story: Fam10 needs more space again. My calculations say it
needs 172 more bytes, give it 512 and hope that's enough for a while.
Trivial.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 22:54:40 +00:00
Myles Watson e3e4981813 Trivial payload location changes for buildrom.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 22:01:55 +00:00
Myles Watson e4c98d2899 These config files are so that buildrom can use these two boards.
Myles

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 21:06:08 +00:00
Myles Watson 3d1d3b23f0 This is the sata irq patch for s2895 and ultra40. It also changes some broken
white space in the s2892 and s2891 mptable.c files.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 20:40:55 +00:00
Myles Watson 0eec1a8e8e Fix irqs for secondary ports on both sata controllers.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 17:55:25 +00:00
Uwe Hermann bb33e4a2fe Detect SMSC SCH5027 (trivial).
This chip seems to be very similar to the SMSC DME1737, for coreboot
purposes it might even work without any code changes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 09:27:18 +00:00
Ward Vandewege c4a4116440 This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port on
secondary controller was ok). There were two problems: the master sata
controller was not being initialized, and the irqs for the secondary ports on
both controllers were not being set in the mptable.

Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.

While all ports work reliably under a recent kernel (2.6.24), sata is about
half as fast as under the proprietary bios, according to bonnie++. That still
needs fixing...

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 00:40:39 +00:00
Marc Jones a74a8ffa07 Clean up and remove late initialization code that is no longer needed.
Pstate intialization has moved to early init because it requires a warm reset.
Add CPUID setup and disable SMM access to late initialization. 
Much of this code is leftover from porting from K8.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 23:32:56 +00:00
Marc Jones f0174b5a9c Find matching settings for each CPUs FID, VID, and P-state registers and initialize them.
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).

The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 23:27:53 +00:00
Marc Jones 8127dc41d1 Update the FAM10 microcode to current versions.
In addition, AP microcode is now updated in early initialization to support errata settings that require it.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 23:20:07 +00:00
Marc Jones c74e362723 Missed this file in the previous check-in, r3248.
Add early MSR and PCI register initialization. 
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code
to the generic Fam10 CPU code.
 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 23:09:34 +00:00
Marc Jones da4ce6b451 Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 22:11:31 +00:00
Uwe Hermann 0ab8cddf02 Add support for a 'bootlog' module to coreinfo.
It displays the coreboot printk buffer in RAM and let's you scroll through it.
This feature is only available for coreboot v3 though, as v2 doesn't have a
printk-buffer feature, yet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 20:19:53 +00:00
Uwe Hermann 16acf8b393 Show index numbers in the NVRAM dump, similar to the PCI config space dump.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 16:56:21 +00:00
Jordan Crouse 5f4410b7dd libpayload: Fix keyboard buglet
This solves the multiple keystroke issue that popped up recently.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-21 22:33:58 +00:00
Christopher Kilgour 7bc63fd2cb This trivial patch adds the SMSC SCH3112 Super I/O chip ID to the
generic SMSC support, and corrects a small typo.

With this patch, coreboot v2 on a mainboard with SCH3112 has been
demonstrated to correctly use the serial port.  No other chip
functions were tested.

Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-19 13:32:19 +00:00
Ed Swierk 5971121009 Replace buildtarget's check for --build-id with something
a bit less awkward (pun intended).

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-18 20:48:22 +00:00
Ed Swierk 68aab269fa Alter buildtarget to invoke the cross-compiler when
checking for --build-id, if the user has specified one by setting CC
in the environment; there's no point in checking the native linker in
this case.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-18 20:47:11 +00:00
Uwe Hermann 8d0a12ac7c Change default payload location for easier buildrom support (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-16 00:46:08 +00:00