Move into src/cpu/dmp/dmp_post_code.h
Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3989
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This permits any software running after the ramstage to tell coreboot that the
boot was successfull.
Change-Id: I6b19160dcf1ea1948360db71d02e344a3bcb44ef
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3992
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
On AMD Trinity and Kabini boards errors similar to the following are
shown.
ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c',line 431
DmiTable:100123f7, AcpiPstatein: 10010129,AcpiSrat:0,AcpiSlit:0, Mce:10010de9,Cmc:10010eab,Alib:1002111c, AcpiIvrs:0 in
agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5
The reason is that on f16kb boards, the CDIT and DMI table are not
created. On f15tn boards, only the DMI table is not created.
Until the root cause is found, disable the table generation to remove
the errors.
Thanks to Wei Hu for debugging and reporting this issue on the list [1].
[1] http://www.coreboot.org/pipermail/coreboot/2013-November/076607.html
CDIT table is not created
Change-Id: I837e3c322bb5331a9b950a72397796a60642c3f3
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4092
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
The power to memory is lost during the the suspend, activate
the 3VSBSW# which switches the power during S3 suspend sequence.
As a result resuming from suspend to RAM works now, but now the
GPP ports of the Hudson southbridge are gone after resume from S3.
The devices 15.0 and 15.1 are disabled (decode as ffff) and
therefore anything behind them too [1].
[1] http://www.coreboot.org/pipermail/coreboot/2013-November/076620.html
fam15tn hudson PCIe GPP ports off after resume
Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4041
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Qemu makes the guest uuid (qemu -uuid $uuid) available
to the guest via fw_cfg. Other smbios fields can be
configured in qemu using the -smbios command line
switch (check the qemu manpage for details).
This patch adds coreboot support for this, so the
values provided by qemu will actually show up in the
smbios table.
Change-Id: Ifd9ae0d02749af4e7070a65eadbd1a9585a8a8e6
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4086
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Starting with release 1.7 qemu provides acpi tables via fw_cfg. Main
advantage is that new (virtual) hardware which needs acpi support
JustWorks[tm] without having to patch & update the firmware (seabios,
coreboot, ...) accordingly.
So if we find acpi tables in fw_cfg try loading them, otherwise fallback
to the builtin acpi tables.
Change-Id: I792232829b870ff6ed8414a3007e0af17f6c4223
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4040
Tested-by: build bot (Jenkins)
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also
change the final configuration. We need to make sure the settings in FchParam
in resume stage are the same as they were in cold boot stage, otherwise the
board can not wake up more than once.
Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180.
(USB keyboard doesn't work when board wakes up. It is not introduced by this
patch. It needs more debugging.)
Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/3932
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
qemu 1.7+ provides a fw_cfg file named "etc/e820" with e820-like entries
for reservations and ram regions. Use it for ram detection if present,
otherwise fallback to the traditional cmos method.
Change-Id: Icac6c99d2a053e59dfdd28e48d1ceb3d56a61bdc
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4030
Tested-by: build bot (Jenkins)
Qemu can provide files using the firmware config interface.
This is used to pass config options, virtual machine config
info and option roms into the guest.
This patch adds support for reading the file index and loading
files from qemu.
Change-Id: I57d4a734527c4117239f355121cf1fb8a390ab0d
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4029
Tested-by: build bot (Jenkins)
Properly build the super i/o .c files. This prevents including
the .c file directly in romstage, which is generally bad practice.
Adding a Makefile and a .h file to include.
Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4014
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove the COM port enable loop. There is no need to
search for the port when it is needed and known by the
GPIO function.
Change-Id: Ie4e533fd9e49ed9ae62b209317b4b9853ff9926a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I382e30c92a4c428ec53dd959a5fda4927797fb9b
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3974
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It is expected this will always be a casted get_top_of_ram() call
on x86, no reason to do that under chipset.
Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3972
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can
resolve this issue.
I have tested on Ubuntu 13.04 with AMD Catalyst 13.4 Proprietary
Linux Display Driver[1].
[1]. http://support.amd.com/us/gpudownload/linux/Pages/radeon_linux.aspx
Change-Id: I5d2dddb1b7469d56cd64e3c1e0f4c6c6f095b4ab
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3934
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can
resolve this issue.
I have tested on Ubuntu 13.04 with latest graphic driver.
Change-Id: I09c19b8925eedee03cfb1d8c0831a84e8aeeba4f
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3937
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Windows 7 cannot find HDMI audio device because of acpi setting.
I have tested on Windows 7. I can play music.
Change-Id: I90ade7e7be79f65783922333c2cbb2d3cc6557ea
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3933
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This reverts commit de1fe7f655.
While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.
Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3960
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
A late for loop may reference over the current array allocation
and corrupt an unrelated global variable. As a quick fix bumb the
size of the array allocation uniformly to 6.
We missed these boards for commit 9c7d73ca because the arrays
had been renamed.
Change-Id: Iff2f2a0090d9302576bc72195d2a3f6fa37ce29a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3954
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Windows 7 cannot find HDMI audio device because of acpi setting.
I have tested on Windows 7. I can play music.
Change-Id: I53177ce00b676824a903a3397d69338e8c1a38af
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3936
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Northbridge code includes these headers, so they all need to
have the same name to allow different combinations of northbridge
and southbridge. This changes the sb900 names to match sb700 &
sb800, and points agesa/family12 and amd/torpedo to the new file
names.
Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Reviewed-on: http://review.coreboot.org/3825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
If romstage does not make cbmem_initialize() call, linker should
optimize the code for CAR migration away.
This simplifies design of CBMEM console by a considerable amount.
As console buffer is now migrated within cbmem_initialize() call there
is no longer need for cbmemc_reinit() call made at end of romstage.
Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig.
If romstage does not make the cbmem_initialize() call, features like
COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during
romstage, but that data will get lost as no CAR migration is
executed.
Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3917
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This retrieves back the value stored with store_initial_timestamp()
in the bootblock for southbridge.
Change-Id: I377c823706c33ed65af023d20d2e4323edd31199
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Assign the lanes correctly to the physical slots
on the motherboard in `PlatformGnbPcie.c`.
• UMI is connected to SB via 4x PCIe bridge 8.
• The blue x16 slot is not shared with DDI and is routed
through PCIe bridge 2.
• The black x8 slot is in fact a x4 slot and uses all 4 GPPs
from the CPU.
• Assume that DDI is on out-of-PCIe-band lanes.
Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Without this coreboot may (depends on the amount of memory) place the
pci bars below 0xb0000000, then the linux kernel goes move them around
so they are inside the window declared in the acpi tables.
This breaks vesafb as the vga framebuffer gets moved after vgabios
initialization. It's also not exactly nice to expect the OS fix our
mess ;)
Change-Id: If6b50ea863958eea71b567ccb7a06c6a28076111
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3927
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Clean whitespace errors that have gotten past lint-stable-003-whitespace
and gerrit review.
Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3920
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The console has already been initialized in the generic bootblock code, and
reinitializing it causes the same banner line to be printed twice and lots of
artifacts in the actual output. This same change had been made to the other
ARM boards but not for beaglebone.
Change-Id: I72e3be1326b1a52b7ec438a44e4fd5f87e4ec717
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3924
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE
which equals cbmem_base, thus no need to pass it as a parameter.
Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3564
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This helper function is for compatibility only for chipsets that do
not implement get_top_of_ram() to support early CBMEM.
Also remove references to globals high_tables_base and _size under
arch/ and from two ARMv7 boards.
Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3902
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Use the new helper function set_top_of_ram() to remove remaining
uses of high_tables_base and _size under northbridge/.
Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3561
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
A late for loop may reference over the current array allocation
and corrupt an unrelated global variable. As a quick fix bumb the
size of the array allocation uniformly to 6.
Change-Id: Ib067fdf077e091d13e32cc3a8e4a0b713d19bcc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3914
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Two new nvram variables control disabling the two non-ME NICs
on the mainboard. This is implemented by disabling their PCIe bridge.
Change-Id: I086f0d79de3ad0b53fa0ec40648d63378070e3bd
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3870
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Collect early timestamps in Lenovo X60’s romstage.
Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then
doing `cbmem --timestamps` should output the timestamps.
Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3587
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
The northbridge defines it already and to the same value.
Change-Id: Ia5d856258fac52ea0b249142f70a89123ca04f82
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3876
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested on Ubuntu 12.10. S3 is supported. No HD Audio.
Mainboard details: http://www.asrock.com/ipc/overview.asp?Model=IMB-A180
Change-Id: I75254194ab5da8e5c61383d8f85aa4e300815637
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3880
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
It still pointed to the old binary despite implementing the newer interface
Change-Id: Iebd5dae98168f5568f3ad6a18c5ebde9abc3ece0
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3869
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Drop unused and commented out variable, and fix a comment while at it.
Change-Id: I1bd7d10aca949c8579433ea1c91264fd816a3fb4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3873
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
