Commit Graph

16 Commits

Author SHA1 Message Date
Furquan Shaikh 79e8412665 util/sconfig: Re-factor sconfig to not assume chip as device
This change adds a new structure "struct chip" to identify elements of
type chip rather than re-using the structure for device. Until now
chip was treated as a device while generating the parse tree and then
device tree postprocessing skipped over all the chip entries in
children and sibling pointers of device nodes.

With this change, the device tree will only contain struct device in
the parsed tree. It helps by avoiding unnecessary pointers to chip
structure as children or next_sibling and then skipping those elements
in post processing. Every device can then hold a pointer to its chip.

When generating static.c, chip structure is emitted before device
structure to ensure that the device structure has chip within its
scope. Externally, the only visible change in static.c should be the
order in which chip/device elements are emitted i.e. previously all
chips under a particular device were emitted to static.c and then the
devices using those chips. Now, all chips are emitted before all the
devices in static.c

BUG=b:80081934
TEST=Verified that abuild is successful for all boards. Also, verified
that static.c generated for eve, kahlee, scarlet, asrock imb_a180 is
unchanged from before in node definitions.

Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05 20:57:16 +00:00
Duncan Laurie bae9f85ddb devicetree: Add USB device type
This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.

A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.

The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.

For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:

     xHCI
       |
    RootHub
    |     |
USB2[0]  USB3[2]

device pci 14.0 on
  chip drivers/usb/acpi
    register "name" = ""Root Hub""
    device usb 0.0 on
      chip drivers/usb/acpi
        register "name" = ""USB 2.0 Port 0""
        device usb 2.0 on end
      end
      chip drivers/usb/acpi
        register "name" = ""USB 3.0 Port 2""
        device usb 3.2 on end
      end
    end
  end
end

Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11 08:59:51 +00:00
Justin TerAvest ca2ed9f450 sconfig: Add a new mmio resource type
Add support for a mmio resource in the devicetree to allow
memory-mapped IO addresses to be assigned to given values.

AMD platforms perform a significant amount of configuration through
these MMIO addresses, including I2C bus configuration.

BUG=b:72121803

Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25 16:50:17 +00:00
Furquan Shaikh e67002968b sconfig: Add a new "SPI" device type
Update sconfig lex and yacc files to add support for a new "SPI" device
type in the devicetree. SPI device takes only parameter i.e. chip select
number for the device on the SPI bus.

Re-generate the shipped files for sconfig using flex 2.6.0 and bison
3.0.4 (make CONFIG_SCONFIG_GENPARSER=1). Clean up local paths that leak
into generated files.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.

Change-Id: If0831e25b3e4ed87827ad92356d7bf47b6387884
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18339
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:41:15 +01:00
Duncan Laurie 4650f5baff sconfig: Add a new generic device type
Add support for a basic generic device in the devicetree to bind to a
device that does not have a specific bus, but may need to be described
in tables for the operating system.  For instance some chips may have
various GPIO connections that need described but do not fall under any
other device.

In order to support this export the basic 'scan_static_bus()' that can
be used in a device_operations->scan_bus() method to scan for the generic
devices.

It has been possible to get a semi-generic device by using a fake PNP
device, but that isn't really appropriate for many devices.

Also Re-generate the shipped files for sconfig.  Use flex 2.6.0 to avoid
everything being rewritten.  Clean up the local paths that leak into the
generated configs.

Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14789
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16 19:49:59 +02:00
Stefan Reinauer 2e78aa5a78 util/sconfig: Fix warnings
and re-generate _shipped files

Change-Id: I7a18824d64d3f6212e8566695376bf97e2196ee2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14733
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-05-08 21:37:36 +02:00
Elyes HAOUAS 52648623e0 Remove empty lines at end of file
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;

Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-08 00:55:07 +02:00
Aaron Durbin ffda804b52 sconfig: add cpu device type
In order to enumerate CPU devices that are non-x86 (read: no lapic)
provide a generic 'cpu' device.

Change-Id: Ifeafdad8076935c3448784e6958117002509acbf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-07 21:03:25 +02:00
Stefan Reinauer 0aa37c488b sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.

Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:07:20 +01:00
Stefan Reinauer 4aff4458f5 sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.

Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 02:00:10 +01:00
Sven Schnelle 0fa50a1990 MPTAPLE: generate from devicetree.cb
This patch adds support for autogenerating the MPTABLE from
devicetree.cb. This is done by a write_smp_table() declared
weak in mpspec.c. If the mainboard doesn't provide it's own
function, this generic implementation is called.

Syntax in devicetree.cb:

ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN>

The ioapic_irq directive can be used in pci and pci_domain
devices. If there's no directive, the autogen code traverses
the tree back to the pci_domain and stops at the first device
which such a directive, and use that information to generate the
entry according to PCI IRQ routing rules.

Change-Id: I4df5b198e8430f939d477c14c798414e398a2027
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1138
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13 08:38:13 +02:00
Sven Schnelle 270a908646 Add subsystemid option to sconfig
Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
PCI and PCI domain devices.

Example:

	device pci 00.0 on
	       subsystemid dead beef
	end

If the user wants to have this ID inherited to all subdevices/functions,
he can add 'inherit', like in the following example:

	device pci 00.0 on
	       subsystemid dead beef inherit
	end

If the user don't want to inherit a Subsystem for a single device, he can
specify 'subsystemid 0 0' on this particular device.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 19:58:15 +00:00
Patrick Georgi 114e7b2990 Split C code in sconfig's parser into a separate file.
Update generated parser files.
Add proper include path for utils.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-05 11:19:50 +00:00
Stefan Reinauer 14e2277962 Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 06:56:47 +00:00
Patrick Georgi 05245ec05b Remove #line statements in processed parser source,
to avoid clutter in revision history.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08 12:59:41 +00:00
Patrick Georgi 7e8c9aa271 Replace sconfig with a C implementation.
(smaller, faster, standard parser generator, no more python)

Provide precompiled parser, so bison and flex are optional dependencies.

Adapt Makefile and abuild (which uses some sconfig file as a
magic path) to match.

Drop python as dependency from README, and add bison and flex
as optional dependencies

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08 11:37:43 +00:00