Commit Graph

34513 Commits

Author SHA1 Message Date
Duncan Laurie 36e6c6f8d2 fw_config: Add firmware configuration interface
This change introduces a new top-level interface for interacting with a
bitmask providing firmware configuration information.

This is motivated by Chromebook mainboards that need to support multiple
different configurations at runtime with the same BIOS.  In these
devices the Embedded Controller provides a bitmask that can be broken
down into different fields and each field can then be broken down into
different options.

The firmware configuration value could also be stored in CBFS and this
interface will look in CBFS first to allow the Embedded Controller value
to be overridden.

The firmware configuration interface is intended to easily integrate
into devicetree.cb and lead to less code duplication for new mainboards
that make use of this feature.

BUG=b:147462631
TEST=this provides a new interface that is tested in subsequent commits

Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02 16:40:04 +00:00
Aaron Durbin 1ebbb165ef cpu/x86/mtrr: add x86_setup_mtrrs_with_detect_no_above_4gb()
There's not a function that is the equivalent to
x86_setup_mtrrs_with_detect() but not solving for above 4GiB.
Provide x86_setup_mtrrs_with_detect_no_above_4gb() which is the
equivalent to x86_setup_mtrrs_with_detect() but instructs the MTRR
solver to not take into account memory above 4GiB.

BUG=b:155426691

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia1b5d67d6f139aaa929e03ddbc394d57dfb949e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41897
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 16:10:13 +00:00
Aaron Durbin e1bf0656af arch/x86/postcar_loader: utilize var_mtrr_context API
Now that there is a generic solution in mtrr subsystem utilize
the API.

BUG=b:155426691,b:155322763

Change-Id: Ie349d5669808928c7470c99d25c57c784174b4e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41850
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 16:10:05 +00:00
Aaron Durbin fa5eded303 cpu/x86/mtrr: add helper for setting multiple MTRRs
Introduce concept of var_mtrr_context object for tracking and
assigning MTRR values. The algorithm is lifted from postcar_loader
code, but it's generalized for different type of users: setting
MSRs explicitly or deferring to a particular caller's desired
actions.

BUG=b:155426691,b:155322763

Change-Id: Ic03b4b617196f04071093bbba4cf28d23fa482d8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02 16:09:58 +00:00
Matt Papageorge a21eae0441 soc/amd/picasso: Install AGESA ACPI tables
AGESA FSP provides additional ACPI tables that are required.

BUG=b:133337564, b:153675915
TEST=Boot trembyle to OS and dump ACPI tables.
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:    * TPM2
TPM2 log created at 0xcc513000
ACPI: added table 4/32, length now 52
ACPI:    * MADT
ACPI: added table 5/32, length now 56
current = cc635af0
Searching for AGESA FSP ACPI Tables
ACPI:    * SSDT (AGESA).
ACPI: added table 6/32, length now 60
ACPI:    * CRAT (AGESA).
ACPI: added table 7/32, length now 64
ACPI:    * ALIB (AGESA).
ACPI: added table 8/32, length now 68
ACPI:    * IVRS (AGESA).
ACPI: added table 9/32, length now 72
ACPI:    * HPET
ACPI: added table 10/32, length now 76
           Copying initialized VBIOS image from 0x000c0000
ACPI:    * VFCT at cc63ca30
ACPI: added table 11/32, length now 80
ACPI: done.
ACPI tables: 102048 bytes.

[    0.042326] ACPI: Early table checksum verification disabled
[    0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4)
[    0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110)
[    0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110)
[    0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110)
[    0.083488] ACPI: FACS 0x00000000CC631240 000040
[    0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110)
[    0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110)
[    0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110)
[    0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110)
[    0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD    AMD CPU  00000001 AMD  00000001)
[    0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD    AMD CRAT 00000001 AMD  00000001)
[    0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD    AmdTable 00000002 MSFT 02000002)
[    0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD    AMD IVRS 00000001 AMD  00000000)
[    0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110)
[    0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110)

Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41804
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 13:52:16 +00:00
Christian Walter 061cd78a1a soc/intel/cannonlake: Add RP configuration settings
Add RP configuration settings like Advanced Error Reporting(AER),
Latency Tolerence Reporting (LTR), Max Payload and Active State Power
Management (ASPM).

Tested on CFL platform

Change-Id: Ifaf0cc86ea412ce246723613f99908946d89ccb0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41679
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 09:39:19 +00:00
Keith Hui 1f572b9276 superio/nuvoton/nct6779d: Open some LDN config registers
The porting of Asus P8Z77-M mainboard required changing certain Super
I/O configuration registers that were ignored in devicetree.cb because
they aren't listed as resources. Add the declaration so they can be
changed.

This change is nowhere near enough as the current structure is
insufficient to allow changing configuration registers in the 0xE?
range, which this board also needs.

TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 are reflected when
inspected using superiotool -d.

Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-02 08:02:48 +00:00
V Sowmya 9eb85b1292 soc/intel/jasperlake: Update camera_clock_ctl.asl to ASL2.0 syntax
This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: I76ec29210ecdde728ce55531d2b6657be87ce9da
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-02 07:50:17 +00:00
V Sowmya 8e6fa57e52 soc/intel/jasperlake: Update gpio_op.asl to ASL2.0 syntax
This change updates gpio_op.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: I3ec442ad85f408135642a112873231ce7d39524e
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-02 07:49:51 +00:00
V Sowmya 2267158776 soc/intel/jasperlake: Update pch_hda.asl to ASL2.0 syntax
This change updates pch_hda.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: I8e965560518decbfafabe9ac06066d28d59240d0
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-02 07:49:33 +00:00
V Sowmya be63cf46e5 soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax
This change updates scs.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-02 07:49:24 +00:00
V Sowmya 4b3995c25f soc/intel/jasperlake: Update platform.asl to ASL2.0 syntax
This change updates platform.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: Ie55bcd9ac2ca746c046ebe05140b2ac291fb0459
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-02 07:49:06 +00:00
Jonathan Zhang 641642e11c vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release
Update Cooperlake-SP (CPX-SP) FSP header files to WW20 release.

As CPX-SP FSP engineering is on-going (the processor Mass Production
is some time in this year). These header files will be adjusted when
changes are necessary with newer FSP release. This commit corresponds
to FSP release WW20 (tag WHITLEY.0.PRB.0016.D.65).

Also update soc/xeon_sp code file and Skylake-SP header file accordingly
to use FsptPort80RouteDisable instead of PcdPort80RouteDisable.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-02 07:48:34 +00:00
Kyösti Mälkki e761497674 mb/asrock/h110m: Select MAINBOARD_HAS_LPC_TPM
Change-Id: I6d6a24cb66a104c549790f039049a17ecbef208f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-02 07:46:45 +00:00
Matt DeVillier 6258ec9f70 mb/purism/librem*: drop EC chip device
CB:35086 exposed that the devicetree listed an EC chip for which there
is no actual driver; the EC is entirely ACPI code (.asl) included by
the board's ec.asl. Remove the unnecessary EC chip driver from both
boards, as well as the unnecessary Kconfig selection for librem_bdw.

Test: build/boot Librem 13v1, 13v4, verify battery info etc still correct.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I5cb0b51881ab8f14e9ec693485f673f4284b5f14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02 07:46:29 +00:00
Johnny Lin 2fc0b1c018 soc/xeon_sp/skx: Define MSR PPIN related registers
These changes are in accordance with the documentation:
[*] page 208-209
    Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
    Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Tested on OCP Tioga Pass.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I5e1de8bcb651fb8ae8b106db1978235b0dd84c47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40523
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:45:54 +00:00
Stefan Ott f01a7696f6 mb/lenovo/x230: Add support for ThinkLight
With this patch, the ThinkLight on the ThinkPad X230 can be controlled
through the OS.  This was initially done for the X201 in f63fbdb6:
mb/lenovo/x201: Add support for ThinkLight.

After applying this patch, the light can be controlled like this:

    echo on >/proc/acpi/ibm/light
    echo off >/proc/acpi/ibm/light

Or through sysfs at /sys/class/leds/tpacpi::thinklight

Change-Id: Idd93b26f52eccb8fc79888f1e45117f26d694291
Signed-off-by: Stefan Ott <stefan@ott.net>
Tested-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40669
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:45:25 +00:00
Elyes HAOUAS cb4672885e sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40809
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:43:48 +00:00
Elyes HAOUAS 729c0695e5 sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02 07:43:31 +00:00
Elyes HAOUAS c5dd57ab65 mb/google/{daisy,veyron{_mickey,_rialto}}: Remove unused 'include <vbe.h>'
Change-Id: I7c0be437e8cb49934913563c6d21056034a50095
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41684
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:43:07 +00:00
Elyes HAOUAS d50cde279b src: Remove unused '#include <cbfs.h>'
Found using:
diff <(git grep -l '#include <cbfs.h>' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode

Also add missing 'include <cbfs.h>' in src/soc/qualcomm/sc7180/qupv3_config.c

Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41682
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:42:56 +00:00
Elyes HAOUAS e83c56ae46 src: Remove unused 'include <fmap.h>'
Change-Id: I79eea0a00c2de54f82b372229381534707a295bb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41681
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:42:40 +00:00
Elyes HAOUAS 0c154af217 src: Remove redundant includes
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>,
<stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes
each time when <types.h> is included.

Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02 07:42:32 +00:00
Elyes HAOUAS 48378e1f8d src: Remove duplicated includes
Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:41:25 +00:00
Elyes HAOUAS a3b02e2818 src: Remove unused 'include <symbols.h>'
Change-Id: Ica355292eeda9c386b49db97f021566d52943d40
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41673
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:40:59 +00:00
Elyes HAOUAS 9ffef56c45 soc/amd/picasso: Remove unused 'include <romstage_handoff.h>'
Change-Id: I07100361705ce421131b8a5d772cb5ba2d8722ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41672
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:40:45 +00:00
Elyes HAOUAS ebddada48d src: Remove unused 'include <bootstate.h>'
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02 07:40:35 +00:00
Elyes HAOUAS fcf7d992bf src: Remove unused 'include <bootmode.h>'
Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:40:28 +00:00
Elyes HAOUAS a685fcb7ce src: Remove unused 'include <arch/smp/mpspec.h>'
Change-Id: If8048586e3693a8e6f63d9dc2800b073bab78628
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:40:08 +00:00
Elyes HAOUAS f2b21f6d42 soc/intel/xeon_sp/skx/soc_util.c: Remove unused <cpu/cpu.h>
Change-Id: I6dd004b417c27ff0b9f7e55557a9670f927d425c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02 07:39:58 +00:00
Elyes HAOUAS 98e360e835 soc/intel/*/bootblock/cpu.c: Drop unused includes
Change-Id: Ide01a922d7d8e500f9a0b507544010706661d7de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40690
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:39:49 +00:00
Elyes HAOUAS 8b08c69386 {icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includes
Drop unused includes and add missing <intelblocks/systemagent.h>.

Change-Id: I06c8b2bf65283c3c1fcd25fdaae298b82fc0e09c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-02 07:39:34 +00:00
Elyes HAOUAS 51a5495841 src: Remove unused '#include <timer.h>'
Change-Id: I57e064d26b215743a1cb06bb6605fc4fe1160876
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41491
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:39:05 +00:00
Elyes HAOUAS 32da3437f9 src: Remove unused '#include <cpu/x86/lapic.h>'
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'.

Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:38:45 +00:00
Keith Hui 9d00242e24 mb/asus/p2b: Add p3b-f IRQ routing to DSDT
Change-Id: Ie4d24eee1cffd65707887dd621e3de873d20cf01
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41097
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:38:00 +00:00
Rocky Phagura c62c98a884 soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and
to check SMI status registers. The architecture of Lewisburg PCH is very
similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.

TEST=build for Tiogapass and check ACPI base. Log message will now show
pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing
to io port 0x500.

Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-02 07:37:08 +00:00
Daniel Gröber a895344936 lockdown: Fix missing spaces in boot log
Change-Id: I414703c53d356c6a69be515596c178997eed82e3
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41748
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:35:43 +00:00
Arthur Heymans 3855a9806e soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size
BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries.

Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02 07:34:56 +00:00
Kyösti Mälkki ad2eb28c10 mb/facebook/fbg1701: Remove C_ENV_BOOTBLOCK_SIZE
Remove the use of C_ENV_BOOTBLOCK_SIZE. Verify the bootblock by reading
the CBFS file instead of directly accessing the datablock.

BUG=None
BRANCH=None
TEST=tested on facebook fbg1701

Change-Id: I4254d681525327c7eec18832586818e9c4e8eb22
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41694
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:27:41 +00:00
Wim Vervoorn 9657fc2bd9 commonlib: Add CBFS_TYPE_BOOTBLOCK
Add CBFS_TYPE_BOOTBLOCK to allow accessing the bootblock as a CBFS file.

BUG=N/A
TEST=build

Change-Id: Ibb03ac3a6cd8711e0402e47335bb8e110c6ef61a
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41824
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:26:44 +00:00
Nico Huber 57bbcb3dff util/sconfig: Move default includes out of emit_chips()
This should make it easier to add more includes.

Change-Id: Ib4a25352901408c2b36de4972391df742a0d8037
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41744
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:20:43 +00:00
Nico Huber d09459fe30 util/sconfig: Refactor and fix add_register()
add_register() contained a duplicate check but only compared the new
key to the first (smallest in order) list member. Fix that and factor
the list handling out so it can be used by other functions.

Change-Id: I5a8346f36fa024351e1282c9681868ecf451b283
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41743
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:20:12 +00:00
Jonathan Zhang 9b110bf97a drivers/vpd: add VPD region VPD_RW_THEN_RO
This change is based on the concept that system user's (overwrite)
settings are held in VPD_RW region, while system owner's (default)
settings are held in VPD_RO region.

Add VPD_RW_THEN_RO region type, so that VPD_RW region is searched
first to get overwrite setting, otherwise VPD_RO region is searched
to get default setting.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Icd7cbd9c3fb2a6b02fc417ad45d7d22ca6795457
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-06-02 07:18:40 +00:00
Jonathan Zhang a9117ed496 drivers/vpd: rename VPD_ANY to VPD_RO_THEN_RW
Rename VPD_ANY to VPD_RO_THEN_RW, to reflect the VPD region search
preference. Update all existing code references for VPD_ANY.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I960688d1f6ab199768107ab73b8a7400a3fdf473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41586
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:18:14 +00:00
Nico Huber b781680d6e cpu/x86/mtrr.h: Get rid of commonlib/helpers.h dependency
We want to use the CACHE_ROM_* macros in linker scripts. Avoid
`commonlib/helpers.h` as it contains an ALIGN() macro definition
that conflicts with the ALIGN keyword in linker scripts.

Change-Id: I3bf20733418ca4135f364a3f6489e74d45e4f466
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:17:23 +00:00
Duncan Laurie 4247ba3628 acpi: Add definitions for device sleep states
The ACPI device sleep states are different from system sleep states
and many places hardcode to specific values that are difficult to
decode without referring to the spec.

Change-Id: If5e732725b775742fd2a9fd0df697e312aa7bf20
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41791
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:16:41 +00:00
Elyes HAOUAS 924fe94075 soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40842
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:15:53 +00:00
John Zhao 5d79a0cc5a mb/google/volteer: Enable TCSS DMA0 for Volteer
This explicitly enables TCSS DMA0 controller and disables
TBT PCIe2 and PCIE3 since they are unused on volteer.

BUG=🅱️146624360
TEST=Built and booted on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 04:41:42 +00:00
Usha P f219b6a2b9 mb/google/dedede: Enable GBB configs for dedede
This patch enables the necessary GBB configs for dedede

BUG=none
BRANCH=none
TEST=GBB Flag value was 0x39 before enabling the required flags
and now it is updated to 0x40b9. Verfied from CPU log.

Change-Id: Ica07c65d6cf23ea859de6aa8413377661547e47a
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2020-06-02 03:33:23 +00:00
Paul Fagerburg af983db3f4 util/mb/google: add templates for dedede boards
Add template directories for the Waddledee and Waddledoo reference
boards of the Dedede baseboard.

BUG=b:157183582
BRANCH=None
TEST=N/A

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ida70a44097334991a93fec8f4933d7f6e39a187b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-02 03:30:26 +00:00