Commit graph

13 commits

Author SHA1 Message Date
Ronald G. Minnich
d469cdab93 Add the CONFIG_ROMS config variable.
Tested under abuild, causes no trouble. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 16:32:01 +00:00
Nikolay Petukhov
9c2255c66c Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*

This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.

Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.

I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.

The pirq.patch for IRQ routing logically consist from of two parts:

First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.

Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.

IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.

Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 16:59:27 +00:00
Stefan Reinauer
f8ee1806ac Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:08:58 +00:00
Marc Jones
a0aaa752dd Artec Group dbe61 mainboard support.
Now uses CAR.
New code for SPD-less memory implementation.
Updated IRQ routing.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-20 23:45:44 +00:00
Peter Stuge
17e27509a0 Fix two boards broken by the large patches of late.
artecgroup/dbe61
Add CONFIG_COMPRESSED_PAYLOAD_NRV2B to Options.lb since it's used in
Config.lb.
Change default for CONFIG_PCI_ROM_RUN to 1 so VGA ROM can run.

technologic/ts5300
Removed CONFIG_CONSOLE_VGA, the embedded board has no VGA without the
development addon card anyways.
Changes to target Config.lb so it actually builds.

Signed-off-by: Peter Stuge <peter@stuge.se>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12 00:28:32 +00:00
Ed Swierk
be13dc72d9 Apply linuxbios-rename-other-payload-options.patch
(Patch 2, refs #14)

Signed-off-by: Ed Swierk <eswierk@arastra.com> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15 12:56:28 +00:00
Ed Swierk
1a7a5b49c5 Apply linuxbios-rename-compressed-payload-options.patch, refs #14
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15 11:42:16 +00:00
Stefan Reinauer
ca6312010d * fix the automatic build system by compressing payloads if possible
and leaving enough room for a real payload (not /dev/null)

  This is a wonderful example why "uses" sucks.

* add Config-abuild.lb for those boards that dont build with 
  the default settings and a real payload:
  arima/hdama, amd/quartet, amd/serengeti_cheetah, ibm/e326

* if lzma is installed and a real payload is used, try compressing
  it. 

* fix a small bug in "abuild --help"

This patch is acked by me because its due to infrastructural changes only.
Flames welcome.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-10 13:30:28 +00:00
Ronald G. Minnich
e8bfbb387c This driver is a mistake, removing it.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-20 16:32:59 +00:00
Ronald G. Minnich
efba85f00e commit moire changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19 19:30:11 +00:00
Carl-Daniel Hailfinger
cba07dd682 additions and mods for lzma.
Signed-off-by: Carl-Daniel Hailfinger
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14 15:12:36 +00:00
Indrek Kruusa
8e3464109e Changelog:
* src/cpu/amd/model_lx/model_lx_init.c
  L2 cache initialization removed (moved to northbridge.c)
* src/include/cpu/amd/lxdef.h 
  more checked values
* src/northbridge/amd/lx/northbridge.c
  L2 cache initialization added
  cpubug() commented out
* src/northbridge/amd/lx/raminit.c
  empty function sdram_set_registers() is in use, don't remove
* src/mainboard/artecgroup/dbe61/Config.lb
  irqmap changes
* src/mainboard/artecgroup/dbe61/irq_tables.c
  tentative changes to irq table (currently not in use)
* src/mainboard/artecgroup/dbe61/mainboard.c
  irq assigned manually to NIC
* src/mainboard/artecgroup/dbe61/Options.lb
  gcc 4.0 is OK
* targets/artecgroup/dbe61/Config.lb
  64K for VSA is OK at moment
 
Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03 16:48:18 +00:00
Ron Minnich
5e9dc23120 This patch adds support for the AMD LX cpu.
There is one global change to pci_ids.h. The rest are changes for LX. I
ran abuild and it is ok.  Not all artec design changes are included as
some of them would adversely affect other mainboards. Indrek will need
to test.


Signed-off-by: Ron Minnich
Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
design. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-28 16:06:16 +00:00