- Move EC send/receive polling code to their own functions
- Add named constants for poll timeouts and delay interval
- Use human-readable timeout values
- Add `send`/`recv` functions which support custom timeouts
- Remove extra 10us delays between polling and performing a given
transaction
- Use constants from `ec.h` for standard EC command opcodes
Tested on a Lenovo Edge E530, which takes similar code paths to
the Lenovo Twist S230u.
Change-Id: Ifda5c030ff81f1046be58aa1fcafdcf71a27cd41
Signed-off-by: Abel Briggs <abelbriggs1@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add Q60 and Q61 events to disable or enable the trackpad. The
support for this Q event was added in Star Labs EC version 1.11
Add Q events Q60 and Q61 which are bound to the F10 key. The event
is select based on the value of 0x14, 0x11 will send Q60 and 0x22
will send Q61. Q60 will pull GPIO_177 to low, consequently disabling
the trackpad and Q61 will reset it to the default configuration.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I091b0eb268d4d6d2109559765be71e2746b85f54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Use 'ENV' consistently and drop the redundant 'STAGE' in the naming.
Change-Id: I51f2a7e70eefad12aa214e92f23e5fd2edf46698
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Set the MAX_CHARGE offset to dead_code_t for boards that don't support
the function. The avoids erroneous values being written to the EC.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I306c8a60818b780ef3bfb842e7fcc4d8500d6b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Some platforms have retimers which can be configured via the EC. Add a
handle to these retimer devices to the Type C connector device, using
devicetree references.
BUG=b:208883648
TEST=Verify disassembled SSDT on brya.
BRANCH=None
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
If set OEM string as "", it shows "Not Specified" with dmidecode.
Use default string if it is empty.
BUG=b:230039300
TEST=set OEM string "" and show google with dmidecode -t 2.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I097e1be696ae974aadc47feb8d0c1dae672a5c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add EC memory layout and Q events for AMD Cezanne based boards, "Byte"
and "Fighter", which both use the ITE 5570E.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OPWE offset didn't exist, but it does now so remove the comment about
this.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4a1310c779002dfb00d01a22437ea223bb406609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Support was created for the NPCE9m5x series, using version 1.1
of the datasheet. The specific model tested was the NPCE985P/G,
on the StarLite Mk IV with version 1.00 of the EC firmware.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Rather than using `ite_`, use `ec_` so the same functions
can be called for different ECs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie61af233f731eb47772af1c82c6abdc515bc89cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since CB:62741, the EC values are backed up to the CMOS when entering
S3, S4 and S5. Consequently, they don't need to be stored when they're
changed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If0ea392afae4a4d3c605cdea3c5896fbff606215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The EC values will be changed when entering S3, S4 or S5, so move
the function that stores the current settings outside of logic
that restricts it to S4 or S5. This means the state isn't lost
when entering S3.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia007a8ad9c08a309489e9f64f1ed311858bfcd10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In most boards, it doesn't write OEM_NAME in CBI to override the
manufacturer name in the SMBIOS table. It' better use the "BIOS_INFO" than "BIOS_ERR"
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently, many Linux drivers use DMI quirks to identify ChromeOS
devices and handle them accordingly: namely they look for the SMBIOS
system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be
coreboot. Historically this was consistently the case, but recent model
ChromeOS devices allow the OEM to set the mainboard manufacturer, which
is also the default system manufacturer. This breaks many DMI quirks,
notably ones used by SOF (sound open firmware) for audio.
To fix this, set the system manufactuer for ChromeOS devices to "Google"
for devices selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID, leaving the OEM
customization in place for the mainboard manufacturer. Since boards
selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID are the only ones overriding
the default mainboard manufacturer, they are the only ones which need
this correction.
Test: build/boot google/bloog with Linux 5.16, verify SOF drivers
correctly detect device as a Chromebook and load the appropriate
audio firmware.
Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62796
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use ECWR function, instead of writing raw values to emem, to avoid a
lack of syncronisation as it uses a mutex.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I90cfd3e1752fe25493bd72ea6bcab1fd9318d2e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I40dc78c743f4201a11ea0c26a8af716cab42b805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I93444cdb96eaf729630b48551d0853511b584634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iabeec47bf492b698f95d86aa2d08ba9caedd75f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.
Switch argument will store the correct value.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic2a83df9a270de6d7bab295e732a6c13accbe17c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62606
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.
Switch argument will store the correct value.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I62e0fc3b6fcae72f2d8eacf37a390b4e4b1f0783
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62605
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.
Switch argument will store the correct value.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62604
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the offsets used for the keyboard backlight control:
ECRAM_KBL_STATE 0x19
ECRAM_KBL_BRIGHTNESS 0x18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I23bac43301635e6b18f1cbd28311e7210b049c70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Guard Max Charge EC write in Kconfig so it's only used on
platforms that support it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When entering suspend, ACPI support is disabled by setting OSFG to 0x00.
This has been moved to be the final action, so it is after saving the
current EC settings.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5705efab42d2fe0fd5abc6c17eeea46ead27db17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use ECRD function, instead of getting raw values from emem, to avoid a
lack of syncronisation as it uses a mutex.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I31113ef9af3a1e171e3e1f226e7adcfa0fbce61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design
Capacity), only report the design capacity. This handles cases where
the battery calibration is incorrect, and the battery runs out before
the OS thinks it's empty.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Support of MENU key (aka hamburger) for Chromebooks with Vivaldi
keyboard
BUG=b:215038215
TEST=manually tested on Anahera device: pressing T13 key opens menu
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change copies ec_commands.h directly from the Chromium OS EC repo,
with the exception of changing the copyright header to SPDX format.
Update to commit hash af9a119
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I1f2a140257d6127fb19bb514bc345466247b7499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Clang does not seem to work with 'fall through' in comments.
Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently, the settings from CMOS were written to the
EC, which was pointless.
Now, when suspending, the EC values are stored in CMOS
when suspending and subsequently restored when waking.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I998d5509cd5e95736468f88663a1423217cf6ddf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Currently only PLD group is used to check USB port number. In the
future, we want to use custom PLD fields, so custom PLD should also be
considered when checking USB port number.
BUG=b:216376040
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Id8076a2a952de61a6f38fbdecd76e991487bf696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Check for situations where a Type C device isn't useful and avoid
creating one for those scenarios.
BUG=b:215199976
TEST=Tested on brya; verified that USBC device is created.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Tested-by: Alyssa Ross <hi@alyssa.is>
Change-Id: I5e1598bd637ec9f50e7bf8dab9e3c757a30b9848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
End all CMOS variable with a C and EC variables with an E.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie0fab6b9dcd805f7b8c9bf8f14b0a799d8f396c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Convert EC_GPI_SCI to Kconfig option with default value of
0x50 that is used by most boards.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
