Commit Graph

17111 Commits

Author SHA1 Message Date
Werner Zeh 1c3b1112fa fsp_baytrail: Fix a possible hanging DisplayPort
On some devices it can happen that DisplayPort TX lanes
do not work properly if the power gate setup is omitted.
If that happens, DisplayPort training will fail and therefore
DisplayPort channel will not work. Both ports are affected.
It seems that not every CPU shows this effect
and those that are affected tend to fail more often in a cold
environment.
With this fix a board that originally shows this failure
was running for over 1000 power cycles without issues.

Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13743
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-25 15:16:44 +01:00
Furquan Shaikh 0155457449 x86/Makefile.inc: Fix redundant addition of memlayout.ld in bootblock
For C_ENVIRONMENT_BOOTBLOCK, memlayout.ld is added by call to
early_x86_stage. Remove redundant addition of memlayout.ld in this
case.

Change-Id: Ibb5ce690ac4e63f7ff5063d5bd04daeeb731e4d7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/13777
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-25 07:16:10 +01:00
Werner Zeh 116485a634 cbfs: Fix compiler error for gcc versions < 4.6
The missing braces for access to a union member
cause an error on gcc versions < 4.6.

Change-Id: I7de14a6d89219f5376f4f969adecfe8014a5a9d8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13776
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-25 06:17:52 +01:00
Paul Menzel 8b831da586 Revert "cbfstool: Silence LZ4 -Wsign-compare warnings"
This reverts commit 17cb0370a7.

It’s the wrong thing to do, to just disable the warning. The code is
fixed for 32-bit user space now in Change-Id
I85bee25a69c432ef8bb934add7fd2e2e31f03662 (commonlib/lz4_wrapper: Use
correct casts to ensure valid calculations), so enable the warning
again.

Change-Id: I6d1c62c7b4875da8053c25e640c03cedf0ff2916
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13772
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-24 19:27:13 +01:00
Paul Menzel 87fe2360c4 commonlib/lz4_wrapper: Use correct casts to ensure valid calculations
Commit 09f2921b (cbfs: Add LZ4 in-place decompression support for
pre-RAM stages) breaks building cbfstool with gcc (Debian 4.9.2-10)
4.9.2 in Debian 8.3 (jessie) with a 32-bit user space. It works fine
in a 64-bit user space.

```
/home/joey/src/coreboot/src/commonlib/lz4_wrapper.c:164:18: note: in expansion of macro 'MIN'
    size_t size = MIN((uint32_t)b.size, dst + dstn - out);
                  ^
/home/joey/src/coreboot/src/commonlib/include/commonlib/helpers.h:29:35: error: signed and unsigned type in conditional expression [-Werror=sign-compare]
 #define MIN(a,b) ((a) < (b) ? (a) : (b))
                                   ^
```

The problem is arithmetic on void*, so explicitly cast to the wanted
types as suggested by user *redi* in #gcc@irc.freenode.net.

Change-Id: I85bee25a69c432ef8bb934add7fd2e2e31f03662
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13771
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-24 19:26:49 +01:00
Martin Roth abf7d4d7e8 kconfig_lint: Fix checks when running in taint mode
The builders run perl scripts in taint mode, and some of the checks
that the kconfig lint script were running were tainted, causing
the script to terminate early when running on the servers.

This checks to see if taint mode is enabled, and untaints the path
if it is.  All external tools (git & grep) must be in
/bin, /usr/bin, or /usr/local/bin.
This also removes the check for unused kconfig files if taint mode
is enabled.

Change-Id: I8d1e1c32275f759d085759fb5d8a6c85d4f99539
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13751
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-02-24 19:24:03 +01:00
Martin Roth 22aa9e3fcc u-boot: Make sure targets aren't duplicated
When U-Boot isn't selected as a payload, two of the targets:
$(project_dir): and $(project_dir)/$(TAG-y) evaluated to the same
value, generating a make warning when running a clean.  By adding
additional text to the file that is created, this is avoided.

Gets rid of these warnings:
Makefile.inc:54: warning: overriding commands for target `u-boot'
Makefile.inc:37: warning: ignoring old commands for target `u-boot'

Change-Id: I4b4df753612b674b3ccde2a757338840be92d1f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-24 19:22:52 +01:00
Lee Leahy bf08da27d5 Documentation/Intel: Add minimal APCI and TempRamExit documentation
Update the documentation to add the minimal ACPI support.  Also add
TempRamExit entry to the FSP features table.

TEST=None

Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13757
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-24 15:55:42 +01:00
Martin Roth d08eb062df xcompile: Add parameter to aid in debugging
There was a report that xcompile wasn't finding the compilers correctly,
so to aid in future debugging, this adds a parameter to show what
xcompile is doing as it runs.

Run from the command line:
./util/xcompile/xcompile --debug

Change-Id: I779cb3de7b4e3f62a2ef2a6245c3538be518870c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-23 18:03:09 +01:00
Julius Werner 17cb0370a7 cbfstool: Silence LZ4 -Wsign-compare warnings
It seems that the exact behavior of -Wsign-compare changes between GCC
versions... some of them like the commonlib/lz4_wrapper.c code, and some
don't. Since we don't have a well-defined HOSTCC toolchain this slipped
through pre-commit testing. Explicitly silence the warning to ensure
cbfstool still builds on all systems.

Change-Id: I43f951301d3f14ce34dadbe58e885b82d21d6353
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13769
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-23 04:52:44 +01:00
David Hendricks 1173bf30fa board_status.sh: Allow user to override coreboot image path
Some users may wish to run this script using a coreboot image
that does get built in the usual build/ directory, for example
if abuild is used to generate the image.

Change-Id: I7e98780f8b7b57ebbf3babd6a289f0e4fd4103d8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/12489
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-23 00:49:16 +01:00
Patrick Rudolph 10104685c5 southbridge/intel/ibexpeak: Use common gpio.c
Use shared gpio code from common folder.
Remove the now unused bd82x6x/gpio.c.

Needs test on real hardware !

Change-Id: Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13616
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-23 00:28:26 +01:00
Patrick Rudolph 273a8dca1f southbridge/intel/lynxpoint: Use common gpio.c
Use shared gpio code from common folder, except for
INTEL_LYNXPOINT_LP, which has it's own gpio code.

Needs test on real hardware !

Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13615
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-23 00:28:06 +01:00
Joe Pillow 9a4881a783 util: Add scripts to download and extract blobs
This turned out really handy when I tried to build coreboot
for my Chromebox.

These scripts can be used to extract System Agent reference code
and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a
Chrome OS recovery image.

crosfirmware.sh downloads a Chrome OS recovery image from the recovery
image server, unpacks it, extracts the firmware update shell archive,
extracts the firmware images from the shell archive.

To download all Chrome OS firmware images, run
$ ./crosfirmware.sh

To download, e.g. the Panther firmware image, run
$ ./crosfirmware.sh panther

extract_blobs.sh extracts the blobs from a Chrome OS firmware image.

Right now it will produce the ME firmware blob, IFD, VGA option rom,
and mrc.bin

Change-Id: I5fb7e14b10e03e18cd360bc35f1dc92e8ed34e63
Signed-off-by: Joe Pillow <joseph.a.pillow@gmail.com>
Reviewed-on: https://review.coreboot.org/13752
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22 22:50:19 +01:00
Julius Werner 09f2921b5d cbfs: Add LZ4 in-place decompression support for pre-RAM stages
This patch ports the LZ4 decompression code that debuted in libpayload
last year to coreboot for use in CBFS stages (upgrading the base
algorithm to LZ4's dev branch to access the new in-place decompression
checks). This is especially useful for pre-RAM stages in constrained
SRAM-based systems, which previously could not be compressed due to
the size requirements of the LZMA scratchpad and bounce buffer. The
LZ4 algorithm offers a very lean decompressor function and in-place
decompression support to achieve roughly the same boot speed gains
(trading compression ratio for decompression time) with nearly no
memory overhead.

For now we only activate it for the stages that had previously not been
compressed at all on non-XIP (read: non-x86) boards. In the future we
may also consider replacing LZMA completely for certain boards, since
which algorithm wins out on boot speed depends on board-specific
parameters (architecture, processor speed, SPI transfer rate, etc.).

BRANCH=None
BUG=None
TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on
Oak to be about ~20ms faster (cutting load times for affected stages
almost in half).

Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13638
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22 21:38:37 +01:00
Julius Werner 0e3d7de741 urara: Increase bootblock size
The urara bootblock is less than a kilobyte from its limit (20K).
There's more than enough space available so increase it to avoid
impeding changes to core code.

Also add some more automated checks to better model the platform's
multiple windows into the same memory region and guard against
accidental overlaps by a seemingly benign change to one window.

Change-Id: I2e535b56d5d1748830ea1e70fd12fd9e87009bce
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13733
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22 21:38:20 +01:00
Julius Werner 862c385f9a memlayout: Add symbols for stage bounds
Stages are inconsistent with other memlayout regions in that they don't
have _<name> and _e<name> symbols defined. We have _program and
_eprogram, but that always only refers to the current stage and
_eprogram marks the actual end of the executable's memory footprint, not
the end of the area allocated in memlayout. Both of these are sometimes
useful to know, so let's add another set of symbols that allow the stage
areas to be treated more similarly to other regions.

Change-Id: I9e8cff46bb15b51c71a87bd11affb37610aa7df9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13737
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22 21:38:07 +01:00
Lee Leahy f7c01aa774 mainboard/intel/galileo: Enable minimal ACPI tables
Enable the minimal ACPI tables.  Initialize the FADT header and provide
an empty DSDT.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   * CONFIG_PAYLOAD_ELF=y
   * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
*  Testing successful if:
   *  Outputs multiple lines of debug serial text

Change-Id: I2e30c8af2994c9f56d9ba4fe6bc35e133b1d2d6b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13759
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22 19:33:04 +01:00
Lee Leahy d3de85cbcc soc/intel/quark: Add the initial pieces required for ACPI tables
Enable ACPI tables
TEST=None

Change-Id: I38b90f54cd9b00b063557c08980e71851bf3059b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13758
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22 19:32:48 +01:00
Werner Zeh 9d0215363d fsp_baytrail: Add full support for iosf access in reg_script
Add all needed functions to fsp_baytrail so that reg_script can
do full iosf access. To keep it simple, this patch synchronises
iosf access between baytrail and fsp_baytrail.

Change-Id: Ic7f52d7d90c0fe3560fa5a5d96f7fc15062d66d1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13742
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-22 19:25:28 +01:00
Patrick Georgi a05d033226 board-status: deal with sanitized paths
Change I9dd8e4027be21363015cd8df9918610e206afce2 replaces
colons with underscores in paths, to improve compatibility of paths.
This breaks any attempt to interpret the timestamp part of the tree
as a timestamp, so revert the change before doing so.

Change-Id: I0e82e4045120700e9b4fcc8c6e54d761068eaea3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/13766
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-22 19:14:37 +01:00
Vladimir Serbinenko f0d39c409b die() when attempting to use bounce buffer on non-i386.
Only i386 has code to support bounce buffer. For others coreboot
would silently discard part of binary which doesn't work and is a hell to debug.

Instead just die.

Change-Id: I37ae24ea5d13aae95f9856a896700a0408747233
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13750
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22 18:38:48 +01:00
Vladimir Serbinenko 4f22267b09 qemu-armv7: Update running instructions.
Change-Id: I04c0cfea5d49eb70969d6ad38d5cb81d70eeaf9b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13753
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22 18:04:28 +01:00
Lee Leahy c7a943397d Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructions
Update the build instructions for CorebootPayloadPkg to target the
Galileo Gen2 platform.

TEST=Build and run on the Galileo Gen2 platform.

Change-Id: I9ca8a67811eff988f81f04d4c01c77115356c050
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13756
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-22 07:06:54 +01:00
Lee Leahy cda71b8dea console: Add higher baud rates
Enable baud rates of 230400, 460800 and 921600.  Leave the default set
to 115200.

TEST=Build and run on Galileo at 921600.

Change-Id: I8e3980f33665bc183b454cf97c68e297f1b0502c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13755
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-22 02:39:07 +01:00
Vladimir Serbinenko 63cf7cd258 Support arm-linux-gnueabi compilers.
Change-Id: I0edbc93807028a091f0f1bcae81a4092538a3422
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13747
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-21 13:04:58 +01:00
Patrick Georgi a7cac0c21d soc/*: fix uart's regwidth specification in cbtables
coreboot passes information about the serial port implementation to
payloads through a cbtables entry.
We set the register width to 1 on most SoCs because that looked as good
a default as any, but checking the uart structs they use, it's 4 for all
of them.

Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13746
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-02-21 12:26:05 +01:00
Patrick Georgi f92c3fb260 optionslist: Don't add a timestamp
The commit description is enough and this avoids hourly updates of the
timestamp by a cron job.

Change-Id: I30e9fcf28caf94edbb816c22bc8fbcb7ab09ae6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13744
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-21 01:46:15 +01:00
Patrick Georgi 2d5d552fa5 board-status: make push-to-wiki more flexible
Change-Id: I952a694f645caf9d9726965e39afc09c6fdce0e3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13741
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-21 01:42:59 +01:00
Patrick Georgi 8a0dae628f board-status: move wiki cookiejar elsewhere
Change-Id: I1240c215f3d6c3934911c096e2ecbabff175d501
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13740
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-21 01:42:44 +01:00
Vladimir Serbinenko f2134f3bab Fix qemu-armv7 memory map
Old map does not work on recent qemu. New map puts coreboot to ROM, so
it behave more like most real machines would.

For details on this map see comment in memlayout.ld

Change-Id: If1f3328b511daca32ba93da5a6d44402508b37e9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-20 07:31:44 +01:00
Patrick Rudolph bd1fdc6e84 nb/intel/sandybridge/raminit: Add XMP support
Some vendors store lower frequency profiles in the regular SPD,
if the SPD contains a XMP profile. To make use of the board's and DIMM's
maximum supported DRAM frequency, try to parse the XMP profile and
use it instead.

Validate the XMP profile to make sure that the installed DIMM count
per channel is supported and the requested voltage is supported.

To reduce complexity only XMP Profile 1 is read.

Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the
default SPD.

Test system:
 * Gigabyte GA-B75M-D3H
 * Intel Pentium CPU G2130

Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13486
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-02-20 05:11:37 +01:00
zbao c3b0b72813 amdfwtool: Postpone the usage of PSP combo directory
If we only need to "combo" two PSP directories into one image,
we can put first address in romsig 0x10 and second one in
romsig 0x14.

If we really need to put three, the 0x14 is the combo directory
which points to multiple level-2 PSP directories.

I guess that two PSP can also use combo directory, with only
one level-2 directory. But nobody seems to do that.

Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-20 04:57:42 +01:00
zbao 6e2f3d1df4 amdfwtool: Fix some fields in PSP level-2 directory
Change-Id: Ib2da7f2210a823fce7f05824e2a2b73d3c0490e9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13738
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-20 04:57:20 +01:00
Ronald G. Minnich 9831244cb8 emulation/qemu-power8: initial mainboard and arch commit
This builds and produces an image.

The next step is to get a 'halt' instruction into the boot block and then attach with qemu.

I can't get the powerpc64le-linux-gnu-ld.bfd to recognize any output arch but
powerpc. That makes no sense to me.

Change-Id: Ia2a5fe07a1457e7b6974ab1473539c7447d7a449
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/13704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-20 04:55:13 +01:00
Damien Zammit 41462bd0c3 nb/amd/amdmct: Add socket specific configuration for FM2
Change-Id: I1088064e5f84fcabcd51e0eaaedfb5074f7fb2b5
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13709
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-02-19 21:27:35 +01:00
Patrick Rudolph a649a543ba nb/intel/sandybridge/raminit: Improve logging
Use printram() in more places and use printk() only where
it makes sense.
Remove spamming "MRd: %x <= %x\n".
Use common syntax for timing output.

Change-Id: I38965967a029994112d7ab63afd4d9968a7728c5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:34:00 +01:00
Lee Leahy f55f3e67be soc/intel/quark: Use single ID value for HSUART1
Use single ID value for HSUART1.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing successful if:
   *  Debug serial output stays enabled after BS_DEV_RESOURCES state

Change-Id: I38eca247f151e67c2b243a8a3bb21d9d1f4603de
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13734
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:24:22 +01:00
Lee Leahy de8c7e39bc Documentation: x86 device tree processing and memory map
Add documentation on:
*  FSP Silicon Init
*  How to start the x86 device tree processing for ramstage
*  Disabling the PCI devices
*  Generic PCI device drivers
*  Memory map support

TEST=None

Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13718
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:24:02 +01:00
Lee Leahy db7410e0a4 Documentation: x86 add EDK2 CorebootPayloadPkg and documentation links
Add EDK2 CorebootPayloadPkg build instructions, EDK2 documentation links
and EDK2 BIOS build instructions.

TEST=None

Change-Id: I236405914c5fa8e33a7826cc4fa60f6dbf0e7724
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13717
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:23:41 +01:00
Patrick Georgi 55fdfca833 cpu/qemu-power8: don't enable it for qemu-x86
Change-Id: I17ba5a85fecf08ab9970a57c7696525287bbc5a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13745
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-02-19 20:03:52 +01:00
Aaron Durbin 152e5a03a1 libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSC
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information
exported in the coreboot tables as the cpu_khz frequency. That
allows get_cpu_speed() not to be called which currently relies
on the 8254 PIT. As certain x86 platforms allow that device
to be optional or turned off for power saving reasons, allow
a path where get_cpu_speed() is no longer called. Additionally,
this approach also allows the libpayload to not duplicate logic
that already exists in coreboot.

BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Confirmed in payload TSC frequency is honored instead of
     using get_cpu_speed().

Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13671
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-19 19:50:25 +01:00
Aaron Durbin e0969aec25 x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.

BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
     libpayload.

Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-19 19:50:10 +01:00
Aaron Durbin f6ada1c307 lib/coreboot_table: add function to allow arch code to add records
Add lb_arch_add_records() to allow the architecture code to
generically hook into the coreboot table generation.

BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed lb_arch_add_records() is
     called when a strong symbol is provided.

Change-Id: I7c69c0ff0801392bbcf5aef586a48388b624afd4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13669
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-19 19:21:15 +01:00
Andrew Waterman 38cd3756b8 RISC-V: Add more debug info to debug printks
Change-Id: I49292e69a5636c675bb8ed7cfe4462ca8189487e
Signed-off-by: Andrew Waterman <waterman@cs.berkeley.edu>
Reviewed-on: https://review.coreboot.org/13736
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2016-02-19 05:42:52 +01:00
Andrew Waterman f16d904192 RISC-V: Make inline asm usage safer
Change-Id: Id547c98e876e9fd64fa4d12239a2608bfd2495d2
Signed-off-by: Andrew Waterman <aswaterman@gmail.com>
Reviewed-on: https://review.coreboot.org/13735
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2016-02-19 05:42:32 +01:00
Ronald G. Minnich deba4e8560 power8: qemu "cpu"
Change-Id: Ib20d88bb208a605b6bf44e6bf7151c24a08549aa
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/13702
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
2016-02-19 05:41:21 +01:00
Martin Roth dbae4d03ef Payloads: Add U-Boot as a coreboot-payload
- Add Kconfig and Makefile options to use U-Boot as a payload.
- Add Kconfig option for extra cbfstool command line arguments.
- Add Kconfig & Makefile option to load the payload as a flat binary.
- Add u-boot directory to .gitignore.

This is currently working for X-86 only.

Graphics worked in U-Boot correctly by initializing the VBIOS and
setting up a console mode.

Tested in QEMU and on Minnowboard Max.  Got into U-Boot, have not
booted an OS yet.

Change-Id: Ia122a4ad7cd7d96107c1552b0376c8106ca8fb92
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/12714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-18 20:53:42 +01:00
Lee Leahy 654fd0703a soc/intel/quark: Enable HSUART1
Enable HSUART1 for debug serial output.  Specify the fixed resources in
the UART driver.  This keeps debug serial output flowing during the rest
of the device initialization.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing successful if:
   *  Debug serial output stays enabled after BS_DEV_RESOURCES state

Change-Id: Ica02e5fece156b21d4a3889284ca467d55c7880d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13730
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18 20:36:53 +01:00
Lee Leahy 535333dd54 soc/intel/quark: Establish the Memory Map
Add ramstage.h to define some of the common header files used by the
drivers in ramstage.

Add northcluster.c, the driver for the memory controller, which defines
the memory map.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing successful if:
   *  Memory map successfully displayed in BS_WRITE_TABLES state

Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13721
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18 20:36:32 +01:00